Datasheet

ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
SNAS080K –JULY 1999–REVISED MARCH 2013 www.ti.com
Converter Electrical Characteristics (continued)
The following specifications apply for V
+
= V
A
+ = V
D
+ = +5.0 V
DC
, V
REF
+ = +4.096 V
DC
, V
REF
− = 0 V
DC
, 12-bit + sign
conversion mode, f
CK
= f
SK
= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
= f
SK
= 5 MHz for
the ADC12030, ADC12032, ADC12034 and ADC12038, R
S
= 25Ω, source impedance for V
REF
+ and V
REF
− ≤ 25Ω, fully-
differential input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Boldface
limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25°C.
(1)(2)(3)
Units
Parameter Test Conditions Typical
(4)
Limits
(5)
(Limits)
On Channel = 5V and Off Channel = 0V −0.01 −0.3 µA (min)
Off Channel Leakage CH0–CH7
and COM Pins
(13)
On Channel = 0V and Off Channel = 5V 0.01 0.3 µA (max)
On Channel = 5V and Off Channel = 0V 0.01 0.3 µA (max)
On Channel Leakage CH0–CH7
and COM Pins
(13)
On Channel = 0V and Off Channel = 5V −0.01 −0.3 µA (min)
MUXOUT1 and MUXOUT2 Leakage
V
MUXOUT
= 5.0V or V
MUXOUT
= 0V 0.01 0.3 µA (max)
Current
R
ON
MUX On Resistance V
IN
= 2.5V and V
MUXOUT
= 2.4V 850 1150 Ω (max)
R
ON
Matching Chan-to-Chan V
IN
= 2.5V and V
MUXOUT
= 2.4V 5 %
Chan-to-Chan Crosstalk V
IN
= 5 V
P-P
, f
IN
= 40 kHz −72 dB
MUX Bandwidth 90 kHz
(13) Channel leakage current is measured after the channel selection.
DC and Logic Electrical Characteristics
The following specifications apply for V
+
= V
A
+ = V
D
+ = +5.0 V
DC
, V
REF
+ = +4.096 V
DC
, V
REF
− = 0 V
DC
, 12-bit + sign
conversion mode, f
CK
= f
SK
= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
= f
SK
= 5 MHz for
the ADC12030, ADC12032, ADC12034 and ADC12038, R
S
= 25Ω, source impedance for V
REF
+ and V
REF
− ≤ 25Ω, fully-
differential input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Boldface
limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25°C.
(1)(2)(3)
Units
Parameter Test Conditions Typical
(4)
Limits
(5)
(Limits)
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
V
IN(1)
Logical “1” Input Voltage V
+
= 5.5V 2.0 V (min)
V
IN(0)
Logical “0” Input Voltage V
+
= 4.5V 0.8 V (max)
I
IN(1)
Logical “1” Input Current V
IN
= 5.0V 0.005 1.0 µA (max)
I
IN(0)
Logical “0” Input Current V
IN
= 0V −0.005 −1.0 µA (min)
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
V
+
= 4.5V, I
OUT
= −360 µA 2.4 V (min)
V
OUT(1)
Logical “1” Output Voltage
V
+
= 4.5V, I
OUT
= − 10 µA 4.25 V (min)
(1) Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V
A
+
or 5V below GND will not damage this device. However, errors in the conversion can occur (if these diodes are forward biased by more
than 50 mV) if the input voltage magnitude of selected or unselected analog input go above V
A
+ or below GND by more than 50 mV. As
an example, if V
A
+ is 4.5 V
DC
, full-scale input voltage must be ≤4.55 V
DC
to ensure accurate conversions.
(2) To ensure accuracy, it is required that the V
A
+ and V
D
+ be connected together to the same power supply with separate bypass
capacitors at each V
+
pin.
(3) With the test condition for V
REF
(V
REF
+ − V
REF
−) given as +4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV.
(4) Typical figures are at T
J
= T
A
= 25°C and represent most likely parametric norm.
(5) Tested limits are specified to AOQL (Average Outgoing Quality Level).
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