Datasheet
ABC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
MUXOUT1
A/DIN1
MUXOUT2
A/DIN2
DGND
V
D
+
CCLK
SCLK
DI
DO
EOC
PD
AGND
VREF+
VREF-
V
A
+
DOR
CS
CONV
RS-232
Interface
+4.096V
+5V
D Q
CLK
7474
1/6 74HC04
1/4 DS14C89
1/4 DS14C89
1/4 DS14C88
+5V
5 MHz
DTR
RTS
CTS
ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
www.ti.com
SNAS080K –JULY 1999–REVISED MARCH 2013
where
• "n" is the ADC's resolution in bits (4)
The effective bits of an actual ADC is found to be:
n(effective) = ENOB = (S/(N + D) - 1.76 / 6.02 (5)
As an example, this device with a differential signed 5V, 1 kHz sine wave input signal will typically have a S/(N +
D) of 77 dB, which is equivalent to 12.5 effective bits.
15.0 AN RS232 SERIAL INTERFACE
Shown on the following page is a schematic for an RS232 interface to any IBM and compatible PCs. The DTR,
RTS, and CTS RS232 signal lines are buffered via level translators and connected to the ADC12038's DI, SCLK,
and DO pins, respectively. The D flip flop drives the CS control line.
Note: V
A
+
, V
D
+
, and V
REF
+
on the ADC12038 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All
logic devices are bypassed with 0.1 µF caps.
Figure 72. Schematic for an RS232 Interface to any IBM and Compatible PCs
The assignment of the RS-232 port is shown below
B7 B6 B5 B4 B3 B2 B1 B0
Input Address 3FE X X X CTS X X X X
COM1
Output Address 3FC X X X 0 X X RTS DTR
A sample program, written in Microsoft QuickBasic, is shown on the next page. The program prompts for data
mode select instruction to be sent to the ADC. This can be found from the Mode Programming table shown
earlier. The data should be entered in “1”s and “0”s as shown in the table with DI0 first. Next, the program
prompts for the number of SCLK cycles required for the programmed mode select instruction. For instance, to
send all “0”s to the ADC, selects CH0 as the +input, CH1 as the −input, 12-bit conversion, and 13-bit MSB first
data output format (if the sign bit was not turned off by a previous instruction). This would require 13 SCLK
periods since the output data format is 13 bits.
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Product Folder Links: ADC12030 ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032 ADC12H034
ADC12H038