Datasheet

ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
SNAS080K –JULY 1999–REVISED MARCH 2013 www.ti.com
1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the exact number of SCLK pulses that the ADC expects.
Not doing so will desynchronize the serial communications to the ADC. When the supply power is first applied to
the ADC, it will expect to see 13 SCLK pulses for each I/O transmission. The number of SCLK pulses that the
ADC expects to see is the same as the digital output word length. The digital output word length is controlled by
the Data Out (DO) format. The DO format maybe changed any time a conversion is started or when the sign bit
is turned on or off. The table below details out the number of clock periods required for different DO formats:
DO Format Number of SCLKs Expected
SIGN OFF 8
8-Bit MSB or LSB First
SIGN ON 9
SIGN OFF 12
12-Bit MSB or LSB First
SIGN ON 13
SIGN OFF 16
16-Bit MSB or LSB first
SIGN ON 17
If erroneous SCLK pulses desynchronize communications, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize the device is a shortcoming of leaving CS low
continuously.
The number of clock pulses required for an I/O exchange may be different for the case when CS is left low
continuously vs. the case when CS is cycled. Take the I/O sequence detailed in Figure 61 (Typical Power Supply
Sequence) as an example. The table below lists the number of SCLK pulses required for each instruction:
Instruction CS Low Continuously CS Strobed
Auto Cal 13 SCLKs 8 SCLKs
Read Status 13 SCLKs 8 SCLKs
Read Status 13 SCLKs 8 SCLKs
12-Bit + Sign Conv 1 13 SCLKs 8 SCLKs
12-Bit + Sign Conv 2 13 SCLKs 13 SCLKs
1.4 Analog Input Channel Selection
The data input at DI also selects the channel configuration (see Table 2, Table 3, Table 4, and Table 5). In
Figure 62 the only times when the channel configuration could be modified is during I/O sequences 1, 4, 5 and 6.
Input channels are reselected before the start of each new conversion. Shown below is the data bit stream
required at DI, during I/O sequence number 4 in Figure 62, to set CH1 as the positive input and CH0 as the
negative input for the different versions of ADCs:
Part DI Data
(1)
Number DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
ADC12H030ADC12030 L H L L H L X X
ADC12H032ADC12032 L H L L H L X X
ADC12H034ADC12034 L H L L L H L X
ADC12H038ADC12038 L H L L L L H L
(1) X can be a logic high (H) or low (L).
1.5 Power Up/Down
The ADC may be powered down by taking the PD pin HIGH or by the instruction input at DI (see Table 5 and
Table 6, and the Power Up/Down timing diagrams). When the ADC is powered down in this way, the ADC
conversion circuitry is deactivated but the digital I/O circuitry is kept active.
32 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC12030 ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032 ADC12H034
ADC12H038