Datasheet

ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
www.ti.com SNAS080K –JULY 1999–REVISED MARCH 2013
Timing Characteristics
The following specifications apply for V
+
= V
A
+ = V
D
+ = +5.0 V
DC
, V
REF
+ = +4.096 V
DC
, V
REF
− = 0 V
DC
, 12-bit + sign
conversion mode, t
r
= t
f
= 3 ns, f
CK
= f
SK
= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H03, f
CK
= f
SK
=
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
S
= 25Ω, source impedance for V
REF
+ and V
REF
− ≤ 25Ω,
fully-differential input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25°C.
(1)
Typical Limits Units
Parameter Test Conditions
(2) (3)
(Limits)
Hardware Power-Up Time, Time from PD Falling Edge to
t
HPU
140 250 µs (max)
EOC Rising Edge
Software Power-Up Time, Time from Serial Data Clock
t
SPU
140 250 µs (max)
Falling Edge to EOC Rising Edge
t
ACC
Access Time Delay from CS Falling Edge to DO Data Valid 20 50 ns (max)
Set-Up Time of CS Falling Edge to Serial Data Clock Rising
t
SET-UP
30 ns (min)
Edge
t
DELAY
Delay from SCLK Falling Edge to CS Falling Edge 0 5 ns (min)
t
1H
, t
0H
Delay from CS Rising Edge to DO TRI-STATE R
L
= 3k, C
L
= 100 pF 40 100 ns (max)
t
HDI
DI Hold Time from Serial Data Clock Rising Edge 5 15 ns (min)
t
SDI
DI Set-Up Time from Serial Data Clock Rising Edge 5 10 ns (min)
50 ns (max)
t
HDO
DO Hold Time from Serial Data Clock Falling Edge R
L
= 3k, C
L
= 100 pF 25
5 ns (min)
t
DDO
Delay from Serial Data Clock Falling Edge to DO Data Valid 35 50 ns (max)
DO Rise Time, TRI-STATE to High R
L
= 3k, C
L
= 100 pF 10 30 ns (max)
t
RDO
DO Rise Time, Low to High R
L
= 3k, C
L
= 100 pF 10 30 ns (max)
DO Fall Time, TRI-STATE to Low R
L
= 3k, C
L
= 100 pF 12 30 ns (max)
t
FDO
DO Fall Time, High to Low R
L
= 3k, C
L
= 100 pF 12 30 ns (max)
t
CD
Delay from CS Falling Edge to DOR Falling Edge 25 45 ns (max)
Delay from Serial Data Clock Falling Edge to DOR Rising
t
SD
25 45 ns (max)
Edge
C
IN
Capacitance of Logic Inputs 10 pF
C
OUT
Capacitance of Logic Outputs 20 pF
(1) Timing specifications are tested at the TTL logic levels, V
IL
= 0.4V for a falling edge and V
IH
= 2.4V for a rising edge. TRI-STATE output
voltage is forced to 1.4V.
(2) Typical figures are at T
J
= T
A
= 25°C and represent most likely parametric norm.
(3) Tested limits are specified to AOQL (Average Outgoing Quality Level).
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Product Folder Links: ADC12030 ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032 ADC12H034
ADC12H038