Datasheet

ADC1175
www.ti.com SNAS012H –JANUARY 2000–REVISED APRIL 2013
CONVERTER ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for AV
DD
= DV
DD
= +5.0V
DC
, OE = 0V, V
RT
= +2.6V, V
RB
= 0.6V, C
L
= 20 pF, f
CLK
= 20MHz
at 50% duty cycle. Boldface limits apply for T
A
= T
MIN
to T
MAX
; all other limits T
A
= 25°C
(1)(2)
Symbol Parameter Conditions Typical
(3)
Limits
(3)
Units
Power Supply Characteristics
IA
DD
Analog Supply Current DV
DD
= AV
DD
=5.25V 9.5 mA
ID
DD
Digital Supply Current DV
DD
= AV
DD
=5.25V 2.5 mA
DV
DD
AV
DD
=5.25V, f
CLK
= 20 MHz 12 17 mA (max)
IAV
DD
+
Total Operating Current DV
DD
AV
DD
=5.25V, f
CLK
= 30 MHz 13
IDV
DD
DV
DD
= AV
DD
=5.25V, CLK Low
(4)
9.6 mA
DV
DD
= AV
DD
=5.25V, f
CLK
= 20 MHz 60 85 mW (max)
Power Consumption
DV
DD
= AV
DD
=5.25V, f
CLK
= 30 MHz 65 mW
CLK, OE Digital Input Characteristics
V
IH
Logical High Input Voltage DV
DD
= AV
DD
= +5.25V 3.0 V (min)
V
IL
Logical Low Input Voltage DV
DD
= AV
DD
= +5.25V 1.0 V (max)
I
IH
Logical High Input Current V
IH
= DV
DD
= AV
DD
= +5.25V 5 µA
I
IL
Logic Low Input Current V
IL
= 0V, DV
DD
= AV
DD
= +5.25V −5 µA
C
IN
Logic Input Capacitance 5 pF
Digital Output Characteristics
I
OH
High Level Output Current DV
DD
= 4.75V, V
OH
= 2.4V −1.1 mA (max)
I
OL
Low Level Output Current DV
DD
= 4.75V, V
OL
= 0.4V 1.6 mA (min)
DV
DD
= 5.25V
I
OZH
,
Tri-State Leakage Current OE = DV
DD
, V
OL
±20 µA
I
OZL
= 0V or V
OH
= DV
DD
AC Electrical Characteristics
f
C1
Maximum Conversion Rate 30 20 MHz (min)
f
C2
Minimum Conversion Rate 1 MHz
CLK rise to data rising 19.5 ns
t
OD
Output Delay
CLK rise to data falling 16 ns
Pipeline Delay (Latency) 2.5 Clock Cycles
t
DS
Sampling (Aperture) Delay CLK low to acquisition of data 3 ns
t
AJ
Aperture Jitter 30 ps rms
t
OH
Output Hold Time CLK high to data invalid 10 ns
t
EN
OE Low to Data Valid Loaded as in Figure 18 11 ns
t
DIS
OE High to High Z State Loaded as in Figure 18 15 ns
f
IN
= 1.31 MHz, V
IN
= FS - 2 LSB 7.5
f
IN
= 4.43 MHz, V
IN
= FS - 2 LSB 7.3 7.0
ENOB Effective Number of Bits Bits (min)
f
IN
= 9.9 MHz, V
IN
= FS - 2 LSB 7.2
f
IN
= 4.43 MHz, f
CLK
= 30 MHz 6.5
f
IN
= 1.31 MHz, V
IN
= FS - 2 LSB 46.9
f
IN
= 4.43 MHz, V
IN
= FS - 2 LSB 45.7 43
SINAD Signal-to- Noise & Distortion dB (min)
f
IN
= 9.9 MHz, V
IN
= FS - 2 LSB 45.1
f
IN
= 4.43 MHz, f
CLK
= 30 MHz 40.9
f
IN
= 1.31 MHz, V
IN
= FS - 2 LSB 47.6
f
IN
= 4.43 MHz, V
IN
= FS - 2 LSB 46 44
SNR Signal-to- Noise Ratio dB (min)
f
IN
= 9.9 MHz, V
IN
= FS - 2 LSB 46.1
f
IN
= 4.43 MHz, f
CLK
= 30 MHz 42.1
(4) At least two clock cycles must be presented to the ADC1175 after power up. See THE ADC1175 CLOCK for details.
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