Datasheet

ADC1175
SNAS012H –JANUARY 2000–REVISED APRIL 2013 www.ti.com
CONVERTER ELECTRICAL CHARACTERISTICS
The following specifications apply for AV
DD
= DV
DD
= +5.0V
DC
, OE = 0V, V
RT
= +2.6V, V
RB
= 0.6V, C
L
= 20 pF, f
CLK
= 20MHz
at 50% duty cycle. Boldface limits apply for T
A
= T
MIN
to T
MAX
; all other limits T
A
= 25°C
(1)(2)
Symbol Parameter Conditions Typical
(3)
Limits
(3)
Units
DC Accuracy
INL Integral Non Linearity f
CLK
= 20 MHz ±0.5 ±1.3 LSB ( max)
INL Integral Non Linearity f
CLK
= 30 MHz ±1.0 LSB ( max)
DNL Differential Non Linearity f
CLK
= 20 MHz ±0.35 ±0.75 LSB ( max)
DNL Differential Non Linearity f
CLK
= 30 MHz ±1.0 LSB ( max)
Missing Codes 0 (max)
E
OT
Top Offset −24 mV
E
OB
Bottom Offset +37 mV
Video Accuracy
f
in
= 4.43 MHz sine wave
DP Differential Phase Error 0.5 Degree
f
CLK
= 17.7 MHz
f
in
= 4.43 MHz sine wave
DG Differential Gain Error 0.4 %
f
CLK
= 17.7 MHz
Analog Input and Reference Characteristics
V
RB
V (min)
V
IN
Input Range 2.0
V
RT
V (max)
(CLK LOW) 4
C
IN
V
IN
Input Capacitance V
IN
= 1.5V + 0.7Vrms pF
(CLK HIGH) 11
R
IN
R
IN
Input Resistance >1 MΩ
BW Analog Input Bandwidth 120 MHz
R
RT
Top Reference Resistor 360 Ω
200 Ω (min)
R
REF
Reference Ladder Resistance V
RT
to V
RB
300
400 Ω (max)
R
RB
Bottom Reference Resistor 90 Ω
4.8 mA (min)
V
RT
=V
RTS
, V
RB
=V
RBS
7
9.3 mA (max)
I
REF
Reference Ladder Current
5.4 mA (min)
V
RT
=V
RTS
,V
RB
=AV
SS
8
10.5 mA (max)
V
RT
connected to V
RTS
V
RT
Reference Top Self Bias Voltage 2.6 V
V
RB
connected to V
RBS
V
RT
connected to V
RTS
V (min)
Reference Bottom Self Bias 0.55
V
RB
0.6
Voltage 0.65
V
RB
connected to V
RBS
V (max)
V
RT
connected to V
RTS
1.89 V (min)
2
V
RB
connected to V
RBS
2.15 V (max)
V
RTS
-
Self Bias Voltage Delta
V
RBS
V
RT
connected to V
RTS
2.3 V
V
RB
connected to AV
SS
1.0 V (min)
V
RT
- V
RB
Reference Voltage Delta 2
2.8 V (max)
(1) The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this
device. However, errors in the A/D conversion can occur if the input goes above V
DD
or below GND by more than 50 mV. As an
example, if AV
DD
is 4.75V
DC
, the full-scale input voltage must be ≤4.80V
DC
to ensure accurate conversions. See Figure 2.
(2) To ensure accuracy, it is required that AV
DD
and DV
DD
be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at T
J
= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
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