Datasheet

ADC1175

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SNAS012H –JANUARY 2000–REVISED APRIL 2013

Driving the V

pin or the V

pin with devices that can not source or sink the current required by the

ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source

sufficient current into the V

pin and sink sufficient current from the V

pin. If these pins are not driven with

devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of

dynamic performance.

Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate as a

clock source.

Input test signal contains harmonic distortion that interferes with the measurement of dynamic signal to

noise ratio. Harmonic and other interfering signals can be removed by inserting a filter at the signal input.

Suitable filters are shown in Figure 23 and Figure 24. The circuit of Figure 23 has cutoff of about 5.5 MHz and is

suitable for input frequencies of 1 MHz to 5 MHz. The circuit of Figure 24 has a cutoff of about 11 MHz and is

suitable for input frequencies of 5 MHz to 10 MHz. These filters should be driven by a generator of 75 Ohm

source impedance and terminated with a 75 ohm resistor.

Figure 23. 5.5 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input

Use at input frequencies of 5 MHz to 10 MHz.

Figure 24. 11 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input

Not considering the effect on a driven CMOS digital circuit(s) when the ADC1175 is in the power down

mode. Because the ADC1175 output goes into a high impedance state when in the power down mode, any

CMOS device connected to these outputs will have their inputs floating when the ADC is in power down. Should

the inputs of the circuit being driven by the ADC digital outputs float to a level near 2.5V, a CMOS device could

exhibit relative large supply currents as the input stage toggles rapidly. The solution is to use pull-down resistors

at the ADC outputs. The value of these resistors is not critical, as long as they do not cause excessive currents

in the outputs of the ADC1175. Low pull-down resistor values could result in degraded SNR and SINAD

performance of the ADC1175. Values between 5 kΩ and 100 kΩ should work well.

Product Folder Links: ADC1175