Datasheet

ADC1175

SNAS012H –JANUARY 2000–REVISED APRIL 2013

www.ti.com

Generally, analog and digital lines should cross each other at 90 degrees to avoid getting digital noise into the

analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines

should be isolated from ALL other lines, analog and digital. Even the generally accepted 90 degree crossing

should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high

frequencies and at high resolution is obtained with a straight signal path.

Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit

in which they are used. Inductors should not be placed side by side, not even with just a small part of their

bodies being beside each other.

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be

connected to a very clean point in the ground return.

DYNAMIC PERFORMANCE

The ADC1175 is a.c. tested and its dynamic performance is ensured. To meet the published specifications, the

clock source driving the CLK input must be free of jitter. For best a.c. performance, isolating the ADC clock from

any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 22.

Figure 22. Isolating the ADC clock from Digital Circuitry.

It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other

signals. Other signals can introduce jitter into the clock signal.

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 50mV below the ground pins or 50mV above the supply pins. Exceeding these limits on even a

transient basis can cause faulty or erratic operation. It is not uncommon for high speed digital circuits to exhibit

undershoot that goes more than a volt below ground due to improper line termination. A resistor of 50Ω to 100Ω

in series with the offending digital input, located close to the signal source, will usually eliminate the problem.

Care should be taken not to overdrive the inputs of the ADC1175. Such practice may lead to conversion

inaccuracies and even to device damage.

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must

charge for each conversion, the more instantaneous digital current is required from DV

and DGND. These

large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the

digital data outputs (with an 74AC541, for example) may be necessary if the data bus to be driven is heavily

loaded. Dynamic performance can also be improved by adding 47Ω to 100Ω series resistors at each digital

output, reducing the energy coupled back into the converter output pins.

Using an inadequate amplifier to drive the analog input. As explained in THE ANALOG INPUT, the

capacitance seen at the input alternates between 4 pF and 11 pF with the clock. This dynamic capacitance is

more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving device. The

LMH6702, LMH6609, LM6152, LM6154, LM6181 and LM6182 have been found to be excellent devices for

driving the ADC1175 analog input.

Product Folder Links: ADC1175