Datasheet

ADC1175
www.ti.com SNAS012H –JANUARY 2000–REVISED APRIL 2013
APPLICATIONS INFORMATION
THE ANALOG INPUT
The analog input of the ADC1175 is a switch followed by an integrator. The input capacitance changes with the
clock level, appearing as 4 pF when the clock is low, and 11 pF when the clock is high. Since a dynamic
capacitance is more difficult to drive than a fixed capacitance, choose an amplifier that can drive this type of load.
The LMH6702, LMH6609, LM6152, LM6154, LM6181 and LM6182 have been found to be excellent devices for
driving the ADC1175. Do not drive the input beyond the supply rails. Figure 19 shows an example of an input
circuit using the LMH6702.
Driving the analog input with input signals up to 2.8 V
P-P
will result in normal behavior where signals above V
RT
will result in a code of FFh and input voltages below V
RB
will result in an output code of zero. Input signals above
2.8 V
P-P
may result in odd behavior where the output code is not FFh when the input exceeds V
RT
.
REFERENCE INPUTS
The reference inputs V
RT
(Reference Top) and V
RB
(Reference Bottom) are the top and bottom of the reference
ladder. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the
reference input pins should be within the range specified in Operating Ratings (1.0V to AV
DD
for V
RT
and 0V to
(AV
DD
- 1.0V) for V
RB
). Any device used to drive the reference pins should be able to source sufficient current
into the V
RT
pin and sink sufficient current from the V
RB
pin.
The reference ladder can be self-biased by connecting V
RT
to V
RTS
and connecting V
RB
to V
RBS
to provide top
and bottom reference voltages of approximately 2.6V and 0.6V, respectively, with V
CC
= 5.0V. This connection is
shown in Figure 19. If V
RT
and V
RTS
are tied together, but V
RB
is tied to analog ground, a top reference voltage of
approximately 2.3V is generated. The top and bottom of the ladder should be bypassed with 10µF tantalum
capacitors located close to the reference pins.
The reference self-bias circuit of Figure 19 is very simple and performance is adequate for many applications.
Superior performance can generally be achieved by driving the reference pins with a low impedance source.
By forcing a little current into or out of the top and bottom of the ladder, as shown in Figure 20, the top and
bottom reference voltages can be trimmed and performance improved over the self-bias method of Figure 19.
The resistive divider at the amplifier inputs can be replaced with potentiometers. The LMC662 amplifier shown
was chosen for its low offset voltage and low cost. Note that a negative power supply is needed for these
amplifiers if their outputs are required to go slightly negative to force the required reference voltages.
If reference voltages are desired that are more than a few tens of millivolts from the self-bias values, the circuit of
Figure 21 will allow forcing the reference voltages to whatever levels are desired. This circuit provides the best
performance because of the low source impedance of the transistors. Note that the V
RTS
and V
RBS
pins are left
floating.
V
RT
can be anywhere between V
RB
+ 1.0V and the analog supply voltage, and V
RB
can be anywhere between
ground and 1.0V below V
RT
. To minimize noise effects and ensure accurate conversions, the total reference
voltage range (V
RT
- V
RB
) should be a minimum of 1.0V and a maximum of about 2.8V. If V
RB
is not required to
be below about +700mV, the -5V points in Figure 21 can be returned to ground and the negative supply
eliminated.
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