Datasheet

ADC1173
www.ti.com SNAS025F –FEBRUARY 1999–REVISED APRIL 2013
CONVERTER ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for AV
DD
= DV
DD
= +3.0V
DC
, OE = 0V, V
RT
= +2.0V, V
RB
= 0V, C
L
= 20 pF, f
CLK
= 15MHz at
50% duty cycle. Boldface limits apply for T
A
= T
MIN
to T
MAX
; all other limits T
A
= 25°C
(1) (2)
Symbol Parameter Conditions Typical
(3)
Limits Units
V
RT
connected to V
RTS
, 1.1 µA (min)
1.2
V
RB
connected to V
RBS
1.3 µA (max)
V
RTS
-
Self Bias Voltage Delta
V
RBS
V
RT
connected to V
RTS
,
1.38 V
V
RB
connected to V
SS
1.0 V (min)
V
RT
- V
RB
Reference Voltage Delta 2
V
A
V (max)
Power Supply Characteristics
IA
DD
Analog Supply Current DV
DD
= AV
DD
= 3.6V 6.8 mA
ID
DD
Digital Supply Current DV
DD
= AV
DD
= 3.6V 2.3 mA
DV
DD
AV
DD
= 3.6V, 9.1 11.4 mA
IAV
DD
+
Total Operating Current
IDV
DD
DV
DD
= AV
DD
= 3.6V, CLK Low
(4)
5.8 mA
Power Consumption DV
DD
= AV
DD
= 3.6V 33 41 mW
CLK, OE Digital Input Characteristics
V
IH
Logical High Input Voltage DV
DD
= AV
DD
= 3.6V 2.2 V (min)
V
IL
Logical Low Input Voltage DV
DD
= AV
DD
= 3.6V 0.8 V (max)
I
IH
Logical High Input Current V
IH
= DV
DD
= AV
DD
= 3.6V 5 µA
I
IL
Logic Low Input Current V
IL
= 0V, DV
DD
= AV
DD
= 3.6V −5 µA
C
IN
Logic Input Capacitance 5 pF
Digital Output Characteristics
DV
DD
= 2.7V, I
OH
= −360µA 2.4 V (min)
V
OH
High Level Output Voltage
DV
DD
= 2.7V, I
OH
= −1.1mA 2.1 1.9 V (min)
V
OL
Low Level Output Voltage DV
DD
= 2.7V, I
OL
= 1.6mA 0.32 0.6 V (max)
DV
DD
= 3.6V, OE = DV
DD
,
I
OZH
,
TRI-STATE Leakage Current V
OL
±20 µA
I
OZL
= 0V or V
OH
= DV
DD
AC Electrical Characteristics
f
C1
Maximum Conversion Rate 20 15 MHz (min)
f
C2
Minimum Conversion Rate 1 MHz
CLK rise to data rising 28 ns
t
OD
Output Delay
CLK rise to data falling 24 ns
Pipeline Delay (Latency) 2.5 Clock Cycles
t
DS
Sampling (Aperture) Delay CLK low to acquisition of data 3 ns
t
AJ
Aperture Jitter 30 ps rms
t
OH
Output Hold Time CLK high to data invalid 15 ns
t
EN
OE Low to Data Valid Loaded as in Figure 25 22 ns
t
DIS
OE High to High Z State Loaded as in Figure 25 12 ns
f
IN
= 1.31 MHz 7.7
ENOB Effective Number of Bits f
IN
= 3.58 MHz 7.6 7.0 Bits (min)
f
IN
= 7.5 MHz 7.4
f
IN
= 1.31 MHz 49
SINAD Signal-to- Noise & Distortion f
IN
= 3.58 MHz 47.7 43 dB (min)
f
IN
= 7.5 MHz 46.5
f
IN
= 1.31 MHz 49
SNR Signal-to-Noise Ratio f
IN
= 3.58 MHz 48.7 44 dB (min)
f
IN
= 7.5 MHz 48.0
f
IN
= 1.31 MHz 65
SFDR Spurious Free Dynamic Range f
IN
= 3.58 MHz 55 dB
f
IN
= 7.5 MHz 51
(4) At least two clock cycles must be presented to the ADC1173 after power up. For details, see THE ADC1173 CLOCK.
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