Datasheet

ADC1173

SNAS025F –FEBRUARY 1999–REVISED APRIL 2013

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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)

Symbol Equivalent Circuit Description

No.

CMOS/TTL compatible Digital input that, when low, enables

1 OE the digital outputs of the ADC1173. When high, the outputs

are in a high impedance state.

CMOS/TTL compatible digital clock Input. V

is sampled on

12 CLK

the falling edge of CLK input.

Conversion data digital Output pins. D0 is the LSB, D7 is the

3 thru

D0-D7 MSB. Valid data is output just after the rising edge of the CLK

input. These pins are enabled by bringing the OE pin low.

Positive digital supply pin. Connect to a clean, quiet voltage

source of +3V. AV

and DV

should have a common

11, 13 DV

source and be separately bypassed with a 10µF capacitor

and a 0.1µF ceramic chip capacitor. For more information,

see POWER SUPPLY CONSIDERATIONS.

The ground return for the digital supply. AV

and DV

2, 24 DV

should be connected together close to the ADC1173.

Positive analog supply pin. Connected to a clean, quiet

voltage source of +3V. AV

and DV

should have a

14, 15,

common source and be separately bypassed with a 10 µF

capacitor and a 0.1 µF ceramic chip capacitor. For more

information, see POWER SUPPLY CONSIDERATIONS.

The ground return for the analog supply. AV

and DV

20, 21 AV

should be connected together close to the ADC1173

package.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: ADC1173