Datasheet

ADC1173

SNAS025F –FEBRUARY 1999–REVISED APRIL 2013

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Driving the V

pin or the V

pin with devices that can not source or sink the current required by the

ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source

sufficient current into the V

pin and sink sufficient current from the V

pin. If these pins are not driven with

devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of

dynamic performance.

Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate as a

clock source.

Input test signal contains harmonic distortion that interferes with the measurement of dynamic signal to

noise ratio. Harmonic and other interfering signals can be removed by inserting a filter at the signal input.

Suitable filters are shown in Figure 30 and Figure 31. The circuit of Figure 30 has cutoff of about 5.5 MHz and is

suitable for input frequencies of 1 MHz to 5 MHz. The circuit of Figure 31 has a cutoff of about 11 MHz and is

suitable for input frequencies of 5 MHz to 10 MHz. These filters should be driven by a generator of 75 Ohm

source impedance and terminated with a 75 ohm resistor.

Figure 30. 5.5 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input

Use at Input Frequencies of 5 MHz to 10 MHz

Figure 31. 11 MHz Low Pass filter to Eliminate Harmonics at the Signal Input.

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