Datasheet

ADC1173
SNAS025F –FEBRUARY 1999–REVISED APRIL 2013 www.ti.com
APPLICATIONS INFORMATION
THE ANALOG INPUT
The analog input of the ADC1173 is a switch followed by an integrator. The input capacitance changes with the
clock level, appearing as 4 pF when the clock is low, and 11 pF when the clock is high. Since a dynamic
capacitance is more difficult to drive than a fixed capacitance, choose an amplifier that can drive this type of load.
The LMH6702, LMH6609, LM6152, LM6154, LM6181 and LM6182 have been found to be excellent devices for
driving the ADC1173. Do not drive the input beyond the supply rails.
shows an example of an input circuit using the LM6181. This circuit has both gain and offset adjustments. If you
desire to eliminate these adjustments, you should reduce the signal swing to avoid clipping at the ADC1173
output that can result from normal tolerances of all system components. With no adjustments, the nominal value
for the amplifier feedback resistor is 510Ω and the 5.1k resistor at the inverting input should be changed to 860Ω
and returned to +3V rather than to the Offset Adjust potentiometer.
Driving the analog input with input signals up to 2.8V
P-P
will result in normal behavior where voltages above V
RT
will result in a code of FFh and input voltages below V
RB
will result in an output code of zero. Input signals above
2.8V
P-P
may result in odd behavior where the output code is not FFh when the input exceeds V
RT
.
REFERENCE INPUTS
The reference inputs V
RT
(Reference Top) and V
RB
(Reference Bottom) are the top and bottom of the reference
ladder. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the
reference input pins should be within the range specified in the Operating Ratings table (1.0V to AV
DD
for V
RT
and 0V to (AV
DD
- 1.0V) for V
RB
). Any device used to drive the reference pins should be able to source sufficient
current into the V
RT
pin and sink sufficient current from the V
RB
pin.
The reference ladder can be self-biased by connecting V
RT
to V
RTS
and connecting V
RB
to V
RBS
to provide top
and bottom reference voltages of approximately 1.56V and 0.36V, respectively, with V
CC
= 3.0V. This connection
is shown in Figure 26. If V
RT
and V
RTS
are tied together, but V
RB
is tied to analog ground, a top reference voltage
of approximately 1.38V is generated. The top and bottom of the ladder should be bypassed with 10µF tantalum
capacitors located close to the reference pins.
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