Datasheet

ADC1173
www.ti.com SNAS025F –FEBRUARY 1999–REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The ADC1173 uses a new, unique architecture to achieve 7.4 effective bits at and maintains superior dynamic
performance up to ½ the clock frequency.
The analog signal at V
IN
that is within the voltage range set by V
RT
and V
RB
are digitized to eight bits at up to 20
MSPS. Input voltages below V
RB
will cause the output word to consist of all zeroes. Input voltages above V
RT
will
cause the output word to consist of all ones. V
RT
has a range of 1.0 Volt to the analog supply voltage, AV
DD
,
while V
RB
has a range of 0 to 2.0 Volts. V
RT
should always be at least 1.0 Volt more positive than V
RB
.
If V
RT
and V
RTS
are connected together and V
RB
and V
RBS
are connected together, the nominal values of V
RT
and
V
RB
are 1.56V and 0.36V, respectively. If V
RT
and V
RTS
are connected together and V
RB
is grounded, the nominal
value of V
RT
is 1.38V.
Data is acquired at the falling edge of the clock and the digital equivalent of the data is available at the digital
outputs the pipeline delay (2.5 clock cycles) plus t
OD
later. The ADC1173 will convert as long as the clock signal
is present at pin 12. The Output Enable pin OE, when low, enables the output pins. The digital outputs are in the
high impedance state when the OE pin is high.
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