Datasheet

ADC108S052
SNAS337G –SEPTEMBER 2005–REVISED MARCH 2013 www.ti.com
ADC108S052 Timing Specifications
The following specifications apply for V
A
= V
D
= +2.7V to +5.25V, AGND = DGND = 0V, f
SCLK
= 3.2 MHz to 8 MHz, f
SAMPLE
=
200 ksps to 500 ksps, and C
L
= 50pF. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Limits
Parameter Test Conditions Typ Units
(1)
t
CSH
CS Hold Time after SCLK Rising Edge 0 10 ns (min)
CS Setup Time prior to SCLK Rising
t
CSS
5 10 ns (min)
Edge
t
EN
CS Falling Edge to DOUT enabled 5 30 ns (max)
DOUT Access Time after SCLK Falling
t
DACC
17 27 ns (max)
Edge
DOUT Hold Time after SCLK Falling
t
DHLD
4 ns (typ)
Edge
DIN Setup Time prior to SCLK Rising
t
DS
3 10 ns (min)
Edge
t
DH
DIN Hold Time after SCLK Rising Edge 3 10 ns (min)
t
CH
SCLK High Time 0.4 x t
SCLK
ns (min)
t
CL
SCLK Low Time 0.4 x t
SCLK
ns (min)
DOUT falling 2.4 20 ns (max)
CS Rising Edge to DOUT High-
t
DIS
Impedance
DOUT rising 0.9 20 ns (max)
(1) Tested limits are ensured to AOQL (Average Outgoing Quality Level).
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