Datasheet

IN0
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
IN7
V
A
/2
IN0
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTRO
L
LOGI
C
CHARGE
REDISTRIBUTION
DAC
V
A
/2
SW2
IN7
ADC108S052
www.ti.com SNAS337G –SEPTEMBER 2005–REVISED MARCH 2013
FUNCTIONAL DESCRIPTION
The ADC108S052 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter.
ADC108S052 OPERATION
Simplified schematics of the ADC108S052 in both track and hold operation are shown in Figure 33 and Figure 34
respectively. In Figure 33, the ADC108S052 is in track mode: switch SW1 connects the sampling capacitor to
one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The
ADC108S052 is in this state for the first three SCLK cycles after CS is brought low.
Figure 34 shows the ADC108S052 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC108S052 is in this state for the last thirteen SCLK cycles
after CS is brought low.
Figure 33. ADC108S052 in Track Mode
Figure 34. ADC108S052 in Hold Mode
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