Datasheet

t
CSH
SCLK
CS
t
CSS
CS
t
CONVERT
t
ACQ
t
CH
t
CL
t
EN
t
DH
t
DS
FOUR ZEROS
DB8
DONTC DONTC ADD2 ADD1 ADD0
DONTC
DONTC DONTC
DB9
DB7 DB6
B1
14
87654321
DB0
DIN
DOUT
SCLK
CS
t
DIS
15 16
t
DACC
t
DHLD
TWO ZEROS
8 9 10 11 12 13 14 15 16
Track
Hold
Power Up
ADD2 ADD1 ADD0
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DIN
DOUT
SCLK
CS
Control register
1 2 3 4 5 6 7
1 2 3 4 5 6 7
ADD2 ADD1 ADD0
8
DB9 DB8 DB7
Power
Down
Power Up
Track
Hold
FOUR ZEROS SIX ZEROS
ADC108S022
SNAS338F –SEPTEMBER 2005–REVISED MARCH 2013 www.ti.com
ADC108S022 Timing Specifications (continued)
The following specifications apply for V
A
= V
D
= +2.7V to 5.25V, AGND = DGND = 0V, f
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
=
50 ksps to 200 ksps, and C
L
= 50pF. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Limits
Symbol Parameter Conditions Typical Units
(1)
DOUT falling 2.4 20 ns (max)
CS Rising Edge to DOUT High-
t
DIS
Impedance
DOUT rising 0.9 20 ns (max)
Timing Diagrams
Figure 2. ADC108S022 Operational Timing Diagram
Figure 3. ADC108S022 Serial Timing Diagram
Figure 4. SCLK and CS Timing Parameters
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