Datasheet
ADC108S022
www.ti.com
SNAS338F –SEPTEMBER 2005–REVISED MARCH 2013
ADC108S022 Converter Electrical Characteristics
(1)
(continued)
The following specifications apply for V
A
= V
D
= +2.7V to +5.25V, AGND = DGND = 0V, f
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
=
50 ksps to 200 ksps, and C
L
= 50pF, unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Limits
Symbol Parameter Conditions Typical Units
(2)
V
A
= V
D
= +2.7V to +3.6V,
0.36 0.94 mA (max)
f
SAMPLE
= 200 kSPS, f
IN
= 40 kHz
Total Supply Current
Normal Mode ( CS low)
V
A
= V
D
= +4.75V to +5.25V,
1.28 2.1 mA (max)
f
SAMPLE
= 200 kSPS, f
IN
= 40 kHz
I
A
+ I
D
V
A
= V
D
= +2.7V to +3.6V,
30 nA
f
SCLK
= 0 ksps
Total Supply Current
Shutdown Mode (CS high)
V
A
= V
D
= +4.75V to +5.25V,
60 nA
f
SCLK
= 0 ksps
V
A
= V
D
= +3.0V
1.1 2.8 mW (max)
f
SAMPLE
= 200 kSPS, f
IN
= 40 kHz
Power Consumption
Normal Mode ( CS low)
V
A
= V
D
= +5.0V
6.4 10.5 mW (max)
f
SAMPLE
= 200 kSPS, f
IN
= 40 kHz
P
C
V
A
= V
D
= +3.0V
0.09 µW
f
SCLK
= 0 ksps
Power Consumption
Shutdown Mode (CS high)
V
A
= V
D
= +5.0V
0.30 µW
f
SCLK
= 0 ksps
AC ELECTRICAL CHARACTERISTICS
f
SCLK
MIN Minimum Clock Frequency 0.8 MHz (min)
f
SCLK
Maximum Clock Frequency 16 3.2 MHz (max)
50 ksps (min)
Sample Rate
f
S
Continuous Mode
1000 200 ksps (max)
t
CONVERT
Conversion (Hold) Time 13 SCLK cycles
30 40 % (min)
DC SCLK Duty Cycle
70 60 % (max)
t
ACQ
Acquisition (Track) Time 3 SCLK cycles
Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles
t
AD
Aperture Delay 4 ns
ADC108S022 Timing Specifications
The following specifications apply for V
A
= V
D
= +2.7V to 5.25V, AGND = DGND = 0V, f
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
=
50 ksps to 200 ksps, and C
L
= 50pF. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Limits
Symbol Parameter Conditions Typical Units
(1)
t
CSH
CS Hold Time after SCLK Rising Edge 0 10 ns (min)
CS Setup Time prior to SCLK Rising
t
CSS
5 10 ns (min)
Edge
t
EN
CS Falling Edge to DOUT enabled 5 30 ns (max)
DOUT Access Time after SCLK Falling
t
DACC
17 27 ns (max)
Edge
DOUT Hold Time after SCLK Falling
t
DHLD
4 ns (typ)
Edge
DIN Setup Time prior to SCLK Rising
t
DS
3 10 ns (min)
Edge
t
DH
DIN Hold Time after SCLK Rising Edge 3 10 ns (min)
t
CH
SCLK High Time 0.4 x t
SCLK
ns (min)
t
CL
SCLK Low Time 0.4 x t
SCLK
ns (min)
(1) Tested limits are specified to AOQL (Average Outgoing Quality Level).
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