Datasheet

ADC10731, ADC10732, ADC10734, ADC10738
www.ti.com SNAS081D –MAY 1999–REVISED MARCH 2013
Electrical Characteristics (continued)
The following specifications apply for V
+
= AV
+
= DV
+
= +5.0 V
DC
, V
REF
+ = 2.5 V
DC
, V
REF
− = GND, V
IN
− = 2.5V for Signed
Characteristics, V
IN
− = GND for Unsigned Characteristics and f
CLK
= 2.5 MHz unless otherwise specified. Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25°C.
(1)(2)(3)(4)
Units
Parameter Test Conditions Typ
(5)
Limits
(6)
(Limits)
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
Logical “1” Input Voltage V
+
= 5.5V 2.0 V (min)
V
IN(0)
Logical “0” Input Voltage V
+
= 4.5V 0.8 V (max)
I
IN(1)
Logical “1” Input Current V
IN
= 5.0V 0.005 +2.5 μA (max)
I
IN(0)
Logical “0” Input Current V
IN
= 0V −0.005 −2.5 μA (max)
V
+
= 4.5V, I
OUT
= −360
2.4 V (min)
μA
V
OUT(1)
Logical “1” Output Voltage
V
+
= 4.5V, I
OUT
= −10 μA 4.5 V (min)
V
OUT(0)
Logical “0” Output Voltage V
+
= 4.5V, I
OUT
= 1.6 mA 0.4 V (min)
V
OUT
= 0V −0.1 −3.0 μA (max)
I
OUT
TRI-STATE Output Current
V
OUT
= 5V +0.1 +3.0 μA (max)
+I
SC
Output Short Circuit Source Current V
OUT
= 0V, V
+
= 4.5V −30 −15 mA(min)
−I
SC
Output Short Circuit Sink Current V
OUT
= V
+
= 4.5V 30 15 mA (min)
CS = HIGH, Power Up 0.9 1.3 mA (max)
CS = HIGH, Power Down 0.2 0.4 mA (max)
I
D
+ Digital Supply Current
(10)
CS = HIGH, Power Down,
0.5 50 μA (max)
and CLK Off
CS = HIGH, Power Up 2.7 6.0 mA (max)
I
A
+ Analog Supply Current
(10)
CS = HIGH, Power Down 3 15 μA (max)
V
REF
+ = +2.5V and
I
REF
Reference Input Current 0.6 mA (max)
CS = HIGH, Power Up
AC CHARACTERISTICS
3.0 2.5 MHz
f
CLK
Clock Frequency 5 (max)
kHz (min)
40 %(min)
Clock Duty Cycle
60 %(max)
Clock
12 12
Cycles
t
C
Conversion Time
5 5 μs (max)
Clock
4.5 4.5
Cycles
t
A
Acquisition Time
2 2 μs (max)
14 30 ns (min)
CS Set-Up Time, Set-Up Time from Falling Edge of CS to
t
SCS
(1 t
CLK
(1 t
CLK
Rising Edge of Clock
(max)
− 14 ns) − 30 ns)
DI Set-Up Time, Set-Up Time from Data Valid on DI to
t
SDI
16 25 ns (min)
Rising Edge of Clock
DI Hold Time, Hold Time of DI Data from Rising Edge of
t
HDI
2 25 ns (min)
Clock to Data not Valid on DI
DO Access Time from Rising Edge of CLK When CS is
t
AT
30 50 ns (min)
“Low” during a Conversion
DO or SARS Access Time from CS , Delay from Falling
t
AC
30 70 ns (max)
Edge of CS to Data Valid on DO or SARS
Delay from Rising Edge of Clock to Falling Edge of SARS
t
DSARS
100 200 ns (max)
when CS is “Low”
(10) The voltage applied to the digital inputs will affect the current drain during power down. These devices are tested with CMOS logic
levels (logic Low = 0V and logic High = 5V). TTL levels increase the current, during power down, to about 300 μA.
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