Datasheet

ADC10731, ADC10732, ADC10734, ADC10738
www.ti.com SNAS081D –MAY 1999–REVISED MARCH 2013
Electrical Characteristics
The following specifications apply for V
+
= AV
+
= DV
+
= +5.0 V
DC
, V
REF
+ = 2.5 V
DC
, V
REF
− = GND, V
IN
− = 2.5V for Signed
Characteristics, V
IN
− = GND for Unsigned Characteristics and f
CLK
= 2.5 MHz unless otherwise specified. Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25°C.
(1)(2)(3)(4)
Units
Parameter Test Conditions Typ
(5)
Limits
(6)
(Limits)
SIGNED STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 10 + Sign Bits
TUE Total Unadjusted Error
(7)
±2.0 LSB (max)
INL Positive and Negative Integral Linearity Error ±1.25 LSB (max)
Positive and Negative Full-Scale Error ±1.5 LSB (max)
Offset Error ±1.5 LSB (max)
Offset Error ±0.2 ±1.0 LSB (max)
Power Supply Sensitivity
+ Full-Scale Error V
+
= +5.0V ±10% ±0.2 ±1.0 LSB (max)
− Full-Scale Error ±0.1 ±0.75 LSB (max)
V
IN
+ = V
IN
− = V
IN
where
DC Common Mode Error
(8)
±0.1 ±0.33 LSB (max)
5.0V ≥ V
IN
≥ 0V
Multiplexer Chan to Chan Matching ±0.1 LSB
UNSIGNED STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 10 Bits
TUE Total Unadjusted Error
(7)
V
REF
+ = 4.096V ±0.75 LSB
INL Integral Linearity Error V
REF
+ = 4.096V ±0.50 LSB
Full-Scale Error V
REF
+ = 4.096V ±1.25 LSB (max)
Offset Error V
REF
+ = 4.096V ±1.25 LSB (max)
Offset Error V
+
= +5.0V ±10% ±0.1 LSB
Power Supply Sensitivity
Full-Scale Error V
REF
+ = 4.096V ±0.1 LSB
V
IN
+ = V
IN
− = V
IN
where
DC Common Mode Error
(8)
±0.1 LSB
+5.0V ≥ V
IN
≥ 0V
Multiplexer Channel to Channel Matching V
REF
+ = 4.096V ±0.1 LSB
DYNAMIC SIGNED CONVERTER CHARACTERISTICS
V
IN
= 4.85 V
PP
, and
S/(N+D) Signal-to-Noise Plus Distortion Ratio 67 dB
f
IN
= 1 kHz to 15 kHz
V
IN
= 4.85 V
PP
, and
ENOB Effective Number of Bits 10.8 Bits
f
IN
= 1 kHz to 15 kHz
V
IN
= 4.85 V
PP
, and
THD Total Harmonic Distortion −78 dB
f
IN
= 1 kHz to 15 kHz
V
IN
= 4.85 V
PP
, and
IMD Intermodulation Distortion −85 dB
f
IN
= 1 kHz to 15 kHz
V
IN
= 4.85 V
PP
, where
Full-Power Bandwidth 380 kHz
S/(N + D) Decreases 3 dB
Multiplexer Chan to Chan Crosstalk f
IN
= 15 kHz −80 dB
(1) Two on-chip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop
below ground or one diode drop greater than V
+
supply. Be careful during testing at low V
+
levels (+4.5V), as high level analog inputs
(+5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors In the conversion result. The
specification allows 50 mV forward bias of either diode; this means that as long as the analog V
IN
does not exceed the supply voltage by
more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected
channel. If AV
+
and DV
+
are minimum (4.5 V
DC
) and full scale must be ≤+4.55 V
DC
. See Figure 6
(2) No connection exists between AV
+
and DV
+
on the chip.To ensure accuracy, it is required that the AV
+
and DV
+
be connected together
to a power supply with separate bypass filter at each V
+
pin.
(3) One LSB is referenced to 10 bits of resolution.
(4) All the timing specifications are tested at the TTL logic levels, V
IL
= 0.8V for a falling edge and V
IH
= 2.0V for a rising. TRl-STATE
voltage level is forced to 1.4V.
(5) Typicals are at T
J
= T
A
= 25°C and represent most likely parametric norm.
(6) Tested limits are ensured to AOQL (Average Outgoing Quality Level).
(7) Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
(8) The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels
shorted together.
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