Datasheet

ADC10731, ADC10732, ADC10734, ADC10738
www.ti.com SNAS081D –MAY 1999–REVISED MARCH 2013
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Figure 3. ADC10732 20-Pin SOIC Package Figure 4. ADC10738 24-Pin SOIC Package
See Package Number DW0020B See Package Number DW0024B
Figure 5. SSOP Package
See Package Number DB0020A
Table 1. Pin Descriptions
Pin Name Description
The clock applied to this input controls the successive approximation conversion time
interval, the acquisition time and the rate at which the serial data exchange occurs. The
rising edge loads the information on the DI pin into the multiplexer address shift register. This
CLK address controls which channel of the analog input multiplexer (MUX) is selected. The falling
edge shifts the data resulting from the A/D conversion out on DO. CS enables or disables
the above functions. The clock frequency applied to this input can be between 5 kHz and 3
MHz
This is the serial data input pin. The data applied to this pin is shifted by CLK into the
DI multiplexer address register. Table 2, Table 3, Table 4 show the multiplexer address
assignment.
The data output pin. The A/D conversion result (DB0-SIGN) are clocked out by the failing
DO
edge of CLK on this pin.
This is the chip select input pin. When a logic low is applied to this pin, the rising edge of
CS CLK shifts the data on DI into the address register. This low also brings DO out of TRI-
STATE after a conversion has been completed
This is the power down input pin. When a logic high is applied to this pin the A/D is powered
PD
down. When a low is applied the A/D is powered up.
This is the successive approximation register status output pin. When CS is high this pin is in
SARS TRI-STATE. With CS low this pin is active high when a conversion is in progress and active
low at all other times.
These are the analog inputs of the MUX. A channel input is selected by the address
information at the DI pin, which is loaded on the rising edge of CLK into the address register
(see Table 2, Table 3, Table 4).
CH0–CH7
The voltage applied to these inputs should not exceed AV
+
or go below GND by more than
50 mV. Exceeding this range on an unselected channel will corrupt the reading of a selected
channel.
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