Datasheet

t
CSU
t
CLH
SCLK
CS
SCLK
t
CONVERT
t
ACQ
t
CH
t
CL
t
ACC
t
EN
t
H
t
SU
Z3 Z2 Z1 Z0
DB8
DONT DONTC ADD2 ADD1 ADD0
DONTC
DONTC DONTC
DB9
DB7 DB6
DB0
16
87654321
DIN
DOUT
SCLK
CS
t
DIS
Zero ZeroDB1
151413
Tri-State
ADC104S051
www.ti.com SNAS253G –NOVEMBER 2004–REVISED MARCH 2013
Figure 2. Timing Test Circuit
Figure 3. ADC104S051 Serial Timing Diagram
Figure 4. SCLK and CS Timing Parameters
Specification Definitions
ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold
capacitor to charge up to the input voltage.
APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the
input signal is acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy
from one analog input that appears at the measured analog input.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to
a perfect ADC of this (ENOB) number of bits.
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