Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply VSSOP 10

CS SCLK

DOUT

DIN

IN1

ADC104S051

GND

IN4

IN3 IN2

ADC104S051

www.ti.com

SNAS253G –NOVEMBER 2004–REVISED MARCH 2013

ADC104S051 4 Channel, 200 ksps to 500 ksps, 10-Bit A/D Converter

Check for Samples: ADC104S051

FEATURES

DESCRIPTION

The ADC104S051 is a low-power, four-channel

• Specified Over a Range of Sample Rates.

CMOS 10-bit analog-to-digital converter with a high-

• Four Input Channels

speed serial interface. Unlike the conventional

• Variable Power Management

practice of specifying performance at a single sample

rate only, the ADC104S051 is fully specified over a

• Single Power Supply with 2.7V - 5.25V Range

sample rate range of 200 ksps to 500 ksps. The

converter is based on a successive-approximation

APPLICATIONS

• Portable Systems

circuit. It can be configured to accept up to four input

signals at inputs IN1 through IN4.

• Remote Data Acquisition

• Instrumentation and Control Systems

The output serial data is straight binary, and is

compatible with several standards, such as SPI™,

QSPI™, MICROWIRE, and many common DSP

KEY SPECIFICATIONS

serial interfaces.

• DNL: ± 0.13 LSB (typ)

The ADC104S051 operates with a single supply, that

• INL: + 0.20/−0.10 LSB (typ)

can range from +2.7V to +5.25V. Normal power

• SNR: 62.7 dB (typ)

consumption using a +3V or +5V supply is 2.7 mW

• Power Consumption:

and 8.6 mW, respectively. The power-down feature

reduces the power consumption to just 0.12 µW using

– 3V Supply: 2.7 mW (typ)

a +3V supply, or 0.47 µW using a +5V supply.

– 5V Supply: 8.6 mW (typ)

The ADC104S051 is packaged in a 10-lead VSSOP

package. Operation over the industrial temperature

range of −40°C to +85°C is specified.

Table 1. Pin-Compatible Alternatives by Resolution and Speed

(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC124S021 ADC124S051 ADC124S101

10-bit ADC104S021 ADC104S051 ADC104S101

8-bit ADC084S021 ADC084S051 ADC084S101

(1) All devices are fully pin and function compatible.

Connection Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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ADC104S051 www.ti.com SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 ADC104S051 4 Channel, 200 ksps to 500 ksps, 10-Bit A/D Converter Check for Samples: ADC104S051 FEATURES DESCRIPTION • • • • The ADC104S051 is a low-power, four-channel CMOS 10-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC104S051 is fully specified over a sample rate range of 200 ksps to 500 ksps.
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ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Block Diagram IN1 . . . IN4 MUX T/H 10-Bit SUCCESSIVE APPROXIMATION ADC VA CONTROL LOGIC CS GND GND SCLK DIN DOUT PIN DESCRIPTIONS and EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 10 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 9 DOUT Digital data output.
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ADC104S051 www.ti.com SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Supply Voltage VA −0.3V to VA +0.
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ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com ADC104S051 Converter Electrical Characteristics (1) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits (2) 10 Bits +0.2 +0.
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ADC104S051 www.ti.com SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 ADC104S051 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Typical Limits (2) Units ISOURCE = 200 µA VA − 0.03 VA − 0.5 V (min) ISOURCE = 1 mA VA − 0.1 ISINK = 200 µA 0.03 0.
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ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com ADC104S051 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, , Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions VA = +3.0V −3.5 VA = +5.0V −0.5 VA = +3.0V +4.5 VA = +5.0V +1.5 VA = +3.0V +4 VA = +5.0V +2 VA = +3.0V +16.5 VA = +5.
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ADC104S051 www.ti.com SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 Figure 2. Timing Test Circuit CS tCONVERT tACQ tCH SCLK 1 2 3 4 tEN 6 Z3 tSU DONT Z2 Z1 7 13 8 14 15 DB9 Z0 DB8 16 tDIS tACC tCL DOUT DIN 5 DB7 DB6 DB1 DB0 Tri-State Zero Zero tH DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Figure 3. ADC104S051 Serial Timing Diagram CS tCSU SCLK tCLH SCLK Figure 4.
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ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below VREF+ and is defined as: (1) VFSE = Vmax + 1.5 LSB – VREF+ where Vmax is the voltage at which the transition to the maximum code occurs.
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ADC104S051 www.ti.com SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. DNL - VA = 3.0V INL - VA = 3.0V Figure 5. Figure 6. DNL - VA = 5.0V INL - VA = 5.0V Figure 7. Figure 8. DNL vs. Supply INL vs. Supply Figure 9. Figure 10.
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ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 10 DNL vs. Clock Frequency INL vs. Clock Frequency Figure 11. Figure 12. DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle Figure 13. Figure 14. DNL vs. Temperature INL vs. Temperature Figure 15. Figure 16.
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ADC104S051 www.ti.com SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. SNR vs. Supply THD vs. Supply Figure 17. Figure 18. SNR vs. Clock Frequency THD vs. Clock Frequency Figure 19. Figure 20. SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle Figure 21. Figure 22.
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ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 12 SNR vs. Input Frequency THD vs. Input Frequency Figure 23. Figure 24. SNR vs. Temperature THD vs. Temperature Figure 25. Figure 26. SFDR vs. Supply SINAD vs. Supply Figure 27. Figure 28.
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ADC104S051 www.ti.com SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. SFDR vs. Clock Frequency SINAD vs. Clock Frequency Figure 29. Figure 30. SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle Figure 31. Figure 32. SFDR vs. Input Frequency SINAD vs. Input Frequency Figure 33. Figure 34.
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ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 14 SFDR vs. Temperature SINAD vs. Temperature Figure 35. Figure 36. ENOB vs. Supply ENOB vs. Clock Frequency Figure 37. Figure 38. ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency Figure 39. Figure 40.
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ADC104S051 www.ti.com SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated. ENOB vs. Temperature Spectral Response - 3V, 200 ksps Figure 41. Figure 42. Spectral Response - 5V, 200 ksps Spectral Response - 3V, 500 ksps Figure 43. Figure 44. Spectral Response - 5V, 500 ksps Power Consumption vs. Throughput Figure 45. Figure 46.
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ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION ADC104S051 OPERATION The ADC104S051 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Simplified schematics of the ADC104S051 in both track and hold modes are shown in Figure 47 Figure 48, respectively.
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ADC104S051 www.ti.com SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting on the 5th clock.
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ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com 111...111 ADC CODE 111...110 111...000 | | 1LSB = VA/1024 011...111 000...010 | 000...001 000...000 0V 0.5LSB +VA - 1.5LSB ANALOG INPUT Figure 49. Ideal Transfer Characteristic TYPICAL APPLICATION CIRCUIT A typical application of the ADC104S051 is shown in Figure 50. Power is provided in this example by the Texas Instruments LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages.
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ADC104S051 www.ti.com SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 VA D1 R1 C2 30 pF VIN C1 3 pF D2 Conversion Phase - Switch Open Track Phase - Switch Closed Figure 51. Equivalent Input Circuit DIGITAL INPUTS AND OUTPUTS The ADC104S051's digital output DOUT is limited by, and cannot exceed, the supply voltage, VA. The digital input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted before VA without any latchup risk.
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ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision F (March 2013) to Revision G • 20 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC104S051CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC104S051CIMMX/NOP VSSOP B DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC104S051CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 VSSOP DGS 10 3500 367.0 367.0 35.
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