Datasheet

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8
Track Hold
Power Up
Track Hold
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
9 10
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
DIN
DOUT
Power Up
SCLK
CS
Power Down
Control register
Control register
DB9 DB8
DB9 DB8
ADC104S021
SNAS278H –FEBRUARY 2005–REVISED MARCH 2013 www.ti.com
ADC104S021/ADC104S021Q Timing Specifications
(1)
(continued)
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, C
L
= 50 pF, f
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
= 50
ksps to 200 ksps, Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits
(2)
Units
t
H
Data Valid SCLK Hold Time +3 10 ns (min)
t
CH
SCLK High Pulse Width 0.5 x t
SCLK
0.3 x t
SCLK
ns (min)
t
CL
SCLK Low Pulse Width 0.5 x t
SCLK
0.3 x t
SCLK
ns (min)
V
A
= +3.0V 1.7
Output Falling
V
A
= +5.0V 1.2
t
DIS
CS Rising Edge to DOUT High-Impedance 20 ns (max)
V
A
= +3.0V 1.0
Output Rising
V
A
= +5.0V 1.0
Timing Diagrams
Figure 2. Timing Test Circuit
Figure 3. ADC104S021/ADC104S021Q Operational Timing Diagram
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