Datasheet

IN1
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
IN4
2
V
A
IN1
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
IN4
2
V
A
ADC104S021
SNAS278H –FEBRUARY 2005–REVISED MARCH 2013 www.ti.com
APPLICATIONS INFORMATION
ADC104S021/ADC104S021Q OPERATION
For the rest of this document, the ADC104S021/ADC104S021Q will be referred to as ADC104S021.
The ADC104S021/ADC104S021Q is a successive-approximation analog-to-digital converter designed around a
charge-redistribution digital-to-analog converter. Simplified schematics of the ADC104S021/ADC104S021Q in
both track and hold modes are shown in Figure 46 and Figure 47, respectively. In Figure 46, the
ADC104S021/ADC104S021Q is in track mode: switch SW1 connects the sampling capacitor to one of four
analog input channels through the multiplexer, and SW2 balances the comparator inputs. The
ADC104S021/ADC104S021Q is in this state for the first three SCLK cycles after CS is brought low.
Figure 47 shows the ADC104S021/ADC104S021Q in hold mode: switch SW1 connects the sampling capacitor to
ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then
instructs the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the
comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC104S021/ADC104S021Q is in this state for the fourth
through sixteenth SCLK cycles after CS is brought low.
The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of
16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is
clocked into the DIN pin to indicate the multiplexer address for the next conversion.
Figure 46. ADC104S021/ADC104S021Q in Track Mode
Figure 47. ADC104S021/ADC104S021Q in Hold Mode
USING THE ADC104S021/ADC104S021Q
Figure 3 and Figure 4 are shown in Timing Diagrams. CS is chip select, which initiates conversions and frames
the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data.
DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to
be written to the ADC104S021/ADC104S021Q's Control Register is placed on DIN, the serial data input pin. New
data is written to the ADC at DIN with each conversion.
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