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ADC104S021

www.ti.com

SNAS278H –FEBRUARY 2005–REVISED MARCH 2013

ADC104S021/ADC104S021Q 4-Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter

Check for Samples: ADC104S021

FEATURES

DESCRIPTION

The ADC104S021/ADC104S021Q is a low-power,

• Specified over a Range of Sample Rates.

four-channel CMOS 10-bit analog-to-digital converter

• Four Input Channels

with a high-speed serial interface. Unlike the

• Variable Power Management

conventional practice of specifying performance at a

single sample rate only, the

• Single Power Supply with 2.7V - 5.25V Range

ADC104S021/ADC104S021Q is fully specified over a

• ADC104S021Q is AEC-Q100 Grade 3 Qualified

sample rate range of 50 ksps to 200 ksps. The

and is Manufactured on an Automotive Grade

converter is based on a successive-approximation

Flow

• Meets AEC-Q100-011 C2 CDM Classification

circuit. It can be configured to accept up to four input

signals at inputs IN1 through IN4.

APPLICATIONS

The output serial data is straight binary, and is

compatible with several standards, such as SPI™,

• Portable Systems

QSPI™, MICROWIRE, and many common DSP

• Remote Data Acquisition

serial interfaces.

• Instrumentation and Control Systems

The ADC104S021/ADC104S021Q operates with a

• Automotive

single supply, that can range from +2.7V to +5.25V.

Normal power consumption using a +3V or +5V

KEY SPECIFICATIONS

supply is 1.94 mW and 6.9 mW, respectively. The

power-down feature reduces the power consumption

• DNL: ± 0.13 LSB (typ)

to just 0.12 µW using a +3V supply, or 0.47 µW using

• INL: ± 0.13 LSB (typ)

a +5V supply.

• SNR: 61.8 dB (typ)

The ADC104S021/ADC104S021Q is packaged in a

• Power Consumption

10-lead VSSOP package. Operation over the

– 3V Supply: 1.94 mW (typ)

industrial temperature range of −40°C to +85°C is

ensured.

– 5V Supply: 6.9 mW (typ)

Table 1. Pin-Compatible Alternatives by Resolution and Speed

(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC124S021 ADC124S051 ADC124S101

10-bit ADC104S021/ADC104S021Q ADC104S051 ADC104S101

8-bit ADC084S021 ADC084S051 ADC084S101

(1) All devices are fully pin and function compatible.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 ADC104S021/ADC104S021Q 4-Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter Check for Samples: ADC104S021 FEATURES DESCRIPTION • • • • • The ADC104S021/ADC104S021Q is a low-power, four-channel CMOS 10-bit analog-to-digital converter with a high-speed serial interface.
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ADC104S021 SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Connection Diagram CS 1 10 SCLK VA 2 9 DOUT ADC104S021/ DIN IN4 3 ADC104S021Q 8 7 4 IN3 5 6 IN2 GND IN1 Figure 1. 10-Lead VSSOP See DGK Package Block Diagram IN1 . . . MUX IN4 T/H 10-Bit SUCCESSIVE APPROXIMATION ADC VA CONTROL LOGIC CS GND GND SCLK DIN DOUT PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to VA.
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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Supply Voltage VA Voltage on Any Pin to GND −0.3V to VA +0.
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ADC104S021 SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com ADC104S021/ADC104S021Q Converter Electrical Characteristics (1) (2) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 ADC104S021/ADC104S021Q Converter Electrical Characteristics (1)(2) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. Symbol Parameter Conditions Typical IOZH, IOZL TRI-STATE® Leakage Current COUT Limits ±0.
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ADC104S021 SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com ADC104S021/ADC104S021Q Timing Specifications(1) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits +3 (2) Units tH Data Valid SCLK Hold Time tCH SCLK High Pulse Width 0.5 x tSCLK 0.
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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 Figure 4. ADC104S021/ADC104S021Q Serial Timing Diagram CS tCSU SCLK tCLH SCLK Figure 5. SCLK and CS Timing Parameters Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage.
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ADC104S021 SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition).
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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 Typical Performance Characteristics TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. DNL - VA = 3.0V INL - VA = 3.0V Figure 6. Figure 7. DNL - VA = 5.0V INL - VA = 5.0V Figure 8. Figure 9. DNL vs. Supply INL vs. Supply Figure 10. Figure 11.
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ADC104S021 SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. 10 DNL vs. Clock Frequency INL vs. Clock Frequency Figure 12. Figure 13. DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle Figure 14. Figure 15. DNL vs. Temperature INL vs. Temperature Figure 16. Figure 17.
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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. SNR vs. Supply THD vs. Supply Figure 18. Figure 19. SNR vs. Clock Frequency THD vs. Clock Frequency Figure 20. Figure 21. SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle Figure 22. Figure 23.
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ADC104S021 SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. 12 SNR vs. Input Frequency THD vs. Input Frequency Figure 24. Figure 25. SNR vs. Temperature THD vs. Temperature Figure 26. Figure 27. SFDR vs. Supply SINAD vs. Supply Figure 28. Figure 29.
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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. SFDR vs. Clock Frequency SINAD vs. Clock Frequency Figure 30. Figure 31. SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle Figure 32. Figure 33. SFDR vs. Input Frequency SINAD vs. Input Frequency Figure 34. Figure 35.
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ADC104S021 SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. 14 SFDR vs. Temperature SINAD vs. Temperature Figure 36. Figure 37. ENOB vs. Supply ENOB vs. Clock Frequency Figure 38. Figure 39. ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency Figure 40. Figure 41.
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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. ENOB vs. Temperature Spectral Response - 3V, 200 ksps Figure 42. Figure 43. Spectral Response - 5V, 200 ksps Power Consumption vs. Throughput Figure 44. Figure 45.
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ADC104S021 SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION ADC104S021/ADC104S021Q OPERATION For the rest of this document, the ADC104S021/ADC104S021Q will be referred to as ADC104S021. The ADC104S021/ADC104S021Q is a successive-approximation analog-to-digital converter designed around a charge-redistribution digital-to-analog converter. Simplified schematics of the ADC104S021/ADC104S021Q in both track and hold modes are shown in Figure 46 and Figure 47, respectively.
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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a power down state when CS is high, and also between continuous conversion cycles.
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ADC104S021 SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com 111...111 111...000 | | ADC CODE 111...110 1LSB = VA/1024 011...111 000...010 | 000...001 000...000 +VA - 1.5LSB 0.5LSB 0V ANALOG INPUT Figure 48. Ideal Transfer Characteristic TYPICAL APPLICATION CIRCUIT A typical application of the ADC104S021/ADC104S021Q is shown in Figure 49.
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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 The capacitor C1 in Figure 50 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the ADC104S021/ADC104S021Q sampling capacitor, and is typically 30 pF.
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ADC104S021 SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Power Supply Noise Considerations The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC.
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ADC104S021 www.ti.com SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision G (March 2013) to Revision H • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC104S021CIMM Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC104S021CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC104S021CIMM VSSOP DGS 10 1000 210.0 185.0 35.0 ADC104S021CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 ADC104S021CIMMX VSSOP DGS 10 3500 367.0 367.0 35.0 VSSOP DGS 10 3500 367.0 367.0 35.0 VSSOP DGS 10 1000 210.0 185.0 35.0 VSSOP DGS 10 3500 367.0 367.0 35.
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