Datasheet

ADC102S021
www.ti.com SNAS281G –FEBRUARY 2005–REVISED MARCH 2013
ADC102S021 Converter Electrical Characteristics
(1)
(continued)
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, C
L
= 50 pF, f
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
= 50
ksps to 200 ksps, unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Parameter Test Conditions Typ Limits
(1)
Units
DIGITAL OUTPUT CHARACTERISTICS
I
SOURCE
= 200 µA V
A
− 0.03 V
A
− 0.5 V (min)
V
OH
Output High Voltage
I
SOURCE
= 1 mA V
A
− 0.1 V
I
SINK
= 200 µA 0.03 0.4 V (max)
V
OL
Output Low Voltage
I
SINK
= 1 mA 0.1 V
I
OZH
, I
OZL
TRI-STATE Leakage Current ±0.01 ±1 µA (max)
C
OUT
TRI-STATE Output Capacitance 2 4 pF (max)
Output Coding Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (C
L
= 10 pF)
2.7 V (min)
V
A
Supply Voltage
5.25 V (max)
V
A
= +5.25V,
1.3 1.8 mA (max)
f
SAMPLE
= 200 ksps, f
IN
= 40 kHz
Supply Current, Normal Mode
(Operational, CS low)
V
A
= +3.6V,
0.55 0.7 mA (max)
f
SAMPLE
= 200 ksps, f
IN
= 40 kHz
I
A
V
A
= +5.25V,
90 nA
f
SAMPLE
= 0 ksps
Supply Current, Shutdown (CS high)
V
A
= +3.6V,
32 nA
f
SAMPLE
= 0 ksps
V
A
= +5.25V 6.9 9.5 mW (max)
Power Consumption, Normal Mode
(Operational, CS low)
V
A
= +3.6V 1.94 2.5 mW (max)
P
D
V
A
= +5.25V 0.47 µW
Power Consumption, Shutdown (CS
high)
V
A
= +3.6V 0.12 µW
AC ELECTRICAL CHARACTERISTICS
0.8 MHz (min)
f
SCLK
Clock Frequency See
(2)
3.2 MHz (max)
50 ksps (min)
f
S
Sample Rate See
(2)
200 ksps (max)
t
CONV
Conversion Time 13 SCLK cycles
30 % (min)
DC SCLK Duty Cycle f
CLK
= 3.2 MHz 50
70 % (max)
t
ACQ
Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles
Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles
(2) This is the frequency range over which the electrical performance is specified. The device is functional over a wider range which is
specified under Operating Ratings.
ADC102S021 Timing Specifications
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, C
L
= 50 pF, f
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
= 50
ksps to 200 ksps, Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Parameter Test Conditions Typ Limits
(1)
Units
V
A
= +3.0V −3.5
t
CSU
Setup Time SCLK High to CS Falling Edge See
(2)
10 ns (min)
V
A
= +5.0V −0.5
V
A
= +3.0V +4.5
t
CLH
Hold time SCLK Low to CS Falling Edge See
(2)
10 ns (min)
V
A
= +5.0V +1.5
(1) Tested limits are specified to Texas Instrument's AOQL (Average Outgoing Quality Level).
(2) Clock may be either high or low when CS is asserted as long as setup and hold times t
CSU
and t
CLH
are strictly observed.
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