Datasheet

TIME

VOLTAGE

Measured

Battery Voltage

LOW

Limit

ALERT pin

(Active Low)

LOW

HYST

ADC101C021, ADC101C027

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

www.ti.com

Figure 38. Trickle Charge

LAYOUT, GROUNDING, AND BYPASSING

For best accuracy and minimum noise, the printed circuit board containing the ADC101C021 should have

separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.

Both of these planes should be located on the same board layer. A single, solid ground plane is preferred if

digital return current does not flow through the analog ground area. Frequently a single ground plane design will

utilize a "fencing" technique to prevent the mixing of analog and digital ground currents. Separate ground planes

should only be utilized when the fencing technique is inadequate. The separate ground planes must be

connected in one place, preferably near the ADC121C021. Special care is required to guarantee that signals do

not pass over power plane boundaries. Return currents must always have a continuous return path below their

traces.

The ADC101C021 power supply should be bypassed with a 4.7µF and a 0.1µF capacitor as close as possible to

the device with the 0.1µF right at the device supply pin. The 4.7µF capacitor should be a tantalum type and the

0.1µF capacitor should be a low ESL type. The power supply for the ADC101C021 should only be used for

analog circuits.

Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the

board. The clock and data lines should have controlled impedances.

Product Folder Links: ADC101C021 ADC101C027