Datasheet

1 9
ACK
by
ADC
Start by
Master
R/W
ACK
by
Master
Frame 1
Address Byte
from Master
D7 D6 D5 D4 D3 D2 D1 D0
1 9
NACK
by
Master
Stop
by
Master
1 9
D15 D14 D13 D12 D11 D10 D9 D8
ACK
by
Master
Frame 4
Upper Data Byte
from ADC
Frame 5
Lower Data Byte
from ADC
Repeat Frames
4 and 5 for
Continuous Mode
A2 A0A1A3A4A5A6
SCL
SDA
SCL
(continued)
SDA
(continued)
D7 D6 D5 D4 D3 D2 D1 D0
1 9
1 9
D15 D14 D13 D12 D11 D10 D9 D8
ACK
by
Master
Frame 2
Upper Data Byte
from ADC
Frame 3
Lower Data Byte
from ADC
Interface Delay
t
Quiet
8 1us
Interface Delay
t
Quiet
8 1us
ADC101C021, ADC101C027
www.ti.com SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013
QUIET INTERFACE MODE
To improve performance at High Speed, operate the ADC in Quiet Interface Mode. This mode provides improved
INL and DNL performance in I
2
C Hs-Mode (3.4MHz). The Quiet Interface mode provides a maximum throughput
rate of 162ksps. Figure 32 describes how to read the conversion result register in this mode. Basically, the
Master needs to release SCL for at least 1µs before the MSB of every upper data byte. The diagram assumes
that the address pointer register is set to its default value.
Quiet Interface mode will only improve INL and DNL performance in Hs-Mode. Standard and Fast mode
performance is unaffected by the Quiet Interface mode.
Figure 32. Reading in Quiet Interface Mode
TYPICAL APPLICATION CIRCUIT
A typical application circuit is shown in Figure 33. The analog supply is bypassed with a capacitor network
located close to the ADC101C021. The ADC uses the analog supply (V
A
) as its reference voltage, so it is very
important that V
A
be kept as clean as possible. Due to the low power requirements of the ADC101C021, it is
possible to use a precision reference as a power supply.
The bus pull-up resistors (R
P
) should be powered by the controller's supply. It is important that the pull-up
resistors are pulled to the same voltage potential as V
A
. This will ensure that the logic levels of all devices on the
bus are compatible. If the controller's supply is noisy, an appropriate bypass capacitor should be added between
the controller's supply pin and the pull-up resistors. For Hs-mode applications, this bypass capacitance will
improve the accuracy of the ADC.
The value of the pull-up resistors (R
P
) depends upon the characteristics of each particular I
2
C bus. The I
2
C
specification describes how to choose an appropriate value. As a general rule-of-thumb, we suggest using a 1kΩ
resistor for Hs-mode bus configurations and a 5kΩ resistor for Standard or Fast Mode bus configurations.
Depending upon the bus capacitance, these values may or may not be sufficient to meet the timing requirements
of the I
2
C bus specification. Please see the I
2
C specification for further information.
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