Datasheet

1 9 1 9
Ack
by
ADC
Start by
Master
R/W
Ack
by
ADC
Frame 1
Address Byte
from Master
Frame 2
Pointer Byte
from Master
0 0 0 0 P2 P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
1 9
ACK
by
ADC
NACK
by
Master
Stop
by
Master
1 9
Frame 3
Data Byte
from Master
Frame 4
Data Byte
from Master
A2 A0A1A3A4A5A6
SCL
SDA
0
SCL
(continued)
SDA
(continued)
D15 D14 D13 D12 D11 D10 D9 D8
1 9
1 9
Start by
Master
R/W
Frame 1
Address Byte
from Master
D7 D6 D5 D4 D3 D2 D1 D0
1 9
Frame 3
Data Byte
from Master
Stop by
Master
SCL
SDA
Frame 2
Pointer Byte
from Master
ACK
by
ADC
ACK
by
ADC
ACK
by
ADC
A2
A0A1
A3A4A5A6
0 0 0 0 P2 P1 P00
ADC101C021, ADC101C027
SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013 www.ti.com
Writing to an ADC Register
The following diagrams indicate the sequence of actions required for writing to an ADC101C021 Register.
Figure 30. Typical Write to a 1-Byte ADC Register
Figure 31. Typical Write to a 2-Byte ADC Register
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Product Folder Links: ADC101C021 ADC101C027