Datasheet

1 9 1 9
Ack
by
ADC
Start by
Master
R/W
Ack
by
ADC
Frame 1
Address Byte
from Master
Frame 2
Pointer Byte
from Master
0 0 0 0 P2 P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
1 9
ACK
by
ADC
NACK
by
Master
Stop
by
Master
1 9
Frame 3
Address Byte
from Master
Frame 4
Data Byte from
ADC
R/W
A2
A0A1
A3A4A5A6
Repeat
Start by
Master
A2 A0A1A3A4A5A6
SCL
SDA
0
SCL
(continued)
SDA
(continued)
D7 D6 D5 D4 D3 D2 D1 D0
1 9
ACK
by
ADC
Start by
Master
NACK
by
Master
SCL
SDA
Stop
by
Master
1 9
Frame 1
Address Byte
from Master
Frame 2
Data Byte from
ADC
R/W
A2
A0A1
A3A4A5A6
ADC101C021, ADC101C027
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SNAS446D FEBRUARY 2008REVISED FEBRUARY 2013
Reading from a 1-Byte ADC Register
The following diagrams indicate the sequence of actions required for a single Byte read from an ADC101C021
Register.
Figure 28. Typical Read from a 1-Byte ADC Register with Preset Pointer
Figure 29. Typical Pointer Set Followed by Immediate Read of a 1-Byte ADC Register
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Product Folder Links: ADC101C021 ADC101C027