Datasheet

1 9 1 9
Ack
by
ADC
Start by
Master
R/W
Ack
by
ADC
Frame 1
Address Byte
from Master
Frame 2
Pointer Byte
from Master
0 0 0 0 P2 P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
ACK
by
ADC
N/ACK*
by
Master
Stop
by
Master
1 9
D15 D14 D13 D12 D11 D10 D9 D8
ACK
by
Master
Frame 3
Address Byte
from Master
Frame 4
Data Byte from
ADC
Frame 5
Data Byte from
ADC
R/W
A2
A0A1
A3A4A5A6
Repeat Frames
4 & 5 for
Continuous Mode
*Note: In continuous mode, this bit must be an ACK. Immediately
preceding a STOP condition, this bit must be a NACK.
Repeat
Start by
Master
A2 A0A1A3A4A5A6
SCL
SDA
0
SCL
(continued)
SDA
(continued)
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
ACK
by
ADC
Start by
Master
N/ACK*
by
Master
SCL
SDA
Stop
by
Master
1 9
D15 D14 D13 D12 D11 D10 D9 D8
ACK
by
Master
Frame 1
Address Byte
from Master
Frame 2
Data Byte from
ADC
Frame 3
Data Byte from
ADC
R/W
A2
A0A1
A3A4A5A6
Repeat Frames
2 & 3 for
Continuous Mode
*Note: In continuous mode, this bit must be an ACK. Immediately
preceding a STOP condition, this bit must be a NACK.
ADC101C021, ADC101C027
SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013 www.ti.com
Reading from a 2-Byte ADC Register
The following diagrams indicate the sequence of actions required for a 2-Byte read from an ADC101C021
Register.
Figure 26. Typical Read from a 2-Byte ADC Register with Preset Pointer
Figure 27. Typical Pointer Set Followed by Immediate Read of a 2-Byte ADC Register
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Product Folder Links: ADC101C021 ADC101C027