Datasheet

Connection Diagrams
Pin Descriptions
AV
+
This is the positive analog supply. This pin
should be bypassed with a 0.1 µF ceramic ca-
pacitor and a 10 µF tantalum capacitor to the
system analog ground.
DV
+
This is the positive digital supply. This supply
pin also needs to be bypassed with 0.1 µF
ceramic and 10 µF tantalum capacitors to the
system digital ground. AV
+
and DV
+
should be
bypassed separately and tied to same power
supply.
DGND This is the digital ground. All logic levels are
referred to this ground.
V
−
This is the negative analog supply. For unipolar
operation this pin may be tied to the system
analog ground or to a negative supply source.
It should not go above DGND by more than
50 mV. When bipolar operation is required, the
voltage on this pin will limit the analog input’s
negative voltage level. In bipolar operation this
supply pin needs to be bypassed with 0.1 µF
ceramic and 10 µF tantalum capacitors to the
system analog ground.
V
REF
+
,
V
REF
−
These are the positive and negative reference
inputs. The voltage difference between V
REF
+
and V
REF
−
will set the analog input voltage
span.
V
REF
Out This is the internal band-gap voltage reference
output. For proper operation of the voltage ref-
erence, this pin needs to be bypassed with a
330 µF tantalum or electrolytic capacitor.
CS
This is the chip select input. When a logic low
is applied to this pin the WR and RD pins are
enabled.
RD
This is the read control input. When a logic low
is applied to this pin the digital outputs are
enabled and the INT output is reset high.
WR This is the write control input. The rising edge
of the signal applied to this pin selects the
multiplexer channel and initiates a conversion.
INT
This is the interrupt output. A logic low at this
output indicates the completion of a conver-
sion.
CLK This is the clock input. The clock frequency
directly controls the duration of the conversion
time (for example, in the 10-bit bipolar mode
t
C
= 22/f
CLK
) and the acquisition time (t
A
=
6/f
CLK
).
DB0(MA0)
–DB7 (L/R)
These are the digital data inputs/outputs. DB0
is the least significant bit of the digital output
word; DB7 is the most significant bit in the
digital output word (see the Output Data Con-
figuration table). MA0 through MA4 are the
digital inputs for the multiplexer channel selec-
tion (see the Multiplexer Addressing tables).
U/S (Unsigned/Signed), 8/10, (8/10-bit resolu-
tion) and L/R (Left/Right justification) are the
digital input bits that set the A/D’s output word
format and resolution (see the Output Data
Configuration table). The conversion time is
modified by the chosen resolution (see Electri-
cal AC Characteristics table). The lower the
resolution, the faster the conversion will be.
CH0–CH7 These are the analog input multiplexer chan-
nels. They can be configured as single-ended
inputs, differential input pairs, or
pseudo-differential inputs (see the Multiplexer
Addressing tables for the input polarity
assignments).
Dual-in-Line and SO Packages
DS011225-2
Top View
Order Number ADC10154
NS Package Number M24B
Dual-in-Line and SO Packages
DS011225-3
Top View
Order Number ADC10158
NS Package Numbers
M28B or N28B
ADC10154/ADC10158
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