Datasheet

ADC10065
www.ti.com SNAS225H –JULY 2003–REVISED APRIL 2013
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for V
SSA
= V
SSIO
= 0V, V
DDA
= +3.0V, V
DDIO
= +2.5V, V
IN
= 2 V
P-P
,
STBY = 0V, V
REF
= 1.20V (External), f
CLK
= 65 MHz, 50% Duty Cycle, C
L
= 10 pF/pin. Boldface limits apply for T
A
= T
MIN
to
T
MAX
: all other limits T
A
= 25°C.
(1)
Parameter Test Conditions Min Typ Max Units
CLK, DF, STBY, SENSE
Logical “1” Input Voltage 2 V
Logical “0” Input Voltage 0.8 V
Logical “1” Input Current +10 µA
Logical “0” Input Current −10 µA
D0–D9 OUTPUT CHARACTERISTICS
Logical “1” Output Voltage I
OUT
= −0.5 mA V
DDIO
−0.2 V
Logical “0” Output Voltage I
OUT
= 1.6 mA 0.4 V
DYNAMIC CONVERTER CHARACTERISTICS
(2)
f
IN
= 11 MHz 9.4, 9.3 9.6 Bits
ENOB Effective Number of Bits
f
IN
= 32 MHz 9.3, 9.2 9.5 Bits
f
IN
= 11 MHz 58.6, 58 59.6 dB
SNR Signal-to-Noise Ratio
f
IN
= 32 MHz 58.5, 57.9 59.3 dB
f
IN
= 11 MHz 58.3, 57.6 59.4 dB
SINAD Signal-to-Noise Ratio + Distortion
f
IN
= 32 MHz 58, 57.4 59 dB
−75.6,
f
IN
= 11 MHz −90 dBc
−69.7
2nd HD 2nd Harmonic
−72.7,
f
IN
= 32 MHz −82 dBc
−68.9
f
IN
= 11 MHz −66.2, −63 −74 dBc
3rd HD 3rd Harmonic
f
IN
= 32 MHz −65.4,
−72 dBc
−63.3
f
IN
= 11 MHz −66.2, −63 −74 dB
Total Harmonic Distortion (First 6
THD
−65.4,
Harmonics)
f
IN
= 32 MHz −72 dB
−63.3
−75.8,
f
IN
= 11 MHz −80 dBc
−74.5
Spurious Free Dynamic Range
SFDR
(Excluding 2nd and 3rd Harmonic)
−74.4,
f
IN
= 32 MHz −80 dBc
−73.3
(1) The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this
device. However, input errors will be generated if the input goes above V
DDA
or V
DDIO
and below V
SSA
or V
SSIO
. See Figure 2
(2) Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V.
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for V
SSA
= V
SSIO
= 0V, V
DDA
= +3.0V, V
DDIO
= +2.5V, V
IN
= 2 V
P-P
,
STBY = 0V, V
REF
= 1.20V (External), f
CLK
= 65 MHz, 50% Duty Cycle, C
L
= 10 pF/pin. Boldface limits apply for T
A
= T
MIN
to
T
MAX
: all other limits T
A
= 25°C.
(1)
Parameter Test Conditions Min
(2)
Typ
(2)
Max
(2)
Units
CLK, DF, STBY, SENSE
f
CLK
1 Maximum Clock Frequency 65 MHz (min)
f
CLK
2 Minimum Clock Frequency 20 MHz
t
CH
Clock High Time 7.69 ns
t
CL
Clock Low Time 7.69 ns
Conversion Latency 6 Cycles
(1) The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this
device. However, input errors will be generated if the input goes above V
DDA
or V
DDIO
and below V
SSA
or V
SSIO
. See Figure 2
(2) Timing specifications are tested at TTL logic levels, V
IL
= 0.4V for a falling edge, and V
IH
= 2.4V for a rising edge.
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