Datasheet

ADC10065
SNAS225H –JULY 2003–REVISED APRIL 2013 www.ti.com
CLK PIN
The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock
signal in the frequency range indicated in AC Electrical Characteristics with rise and fall times of less than 2 ns.
The trace carrying the clock signal should be as short as possible and should not cross any other signal line,
analog or digital, not even at 90°. The CLK signal also drives an internal state machine. If the CLK is interrupted,
or its frequency is too low, the charge on internal capacitors can dissipate to the point where the accuracy of the
output data will degrade. This is what limits the lowest sample rate. The duty cycle of the clock signal can affect
the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the ADC10065 is
designed to maintain performance over a range of duty cycles. While it is specified and performance is ensured
with a 50% clock duty cycle, performance is typically maintained with minimum clock low and high times
indicated in AC Electrical Characteristics. Both minimum high and low times may not be held simultaneously
STBY PIN
The STBY pin, when high, holds the ADC10065 in a power-down mode to conserve power when the converter is
not being used. The power consumption in this state is 15 mW. The output data pins are undefined in this mode.
Power consumption during power-down is not affected by the clock frequency, or by whether there is a clock
signal present. The data in the pipeline is corrupted while in power down.
DF PIN
The DF (Data Format) pin, when high, forces the ADC10065 to output the 2’s complement data format. When DF
is tied low, the output format is offset binary.
IRS PIN
The IRS (Input Range Select) pin defines the input signal amplitude that will produce a full scale output. Table 1
describes the function of the IRS pin.
Table 1. IRS Pin Functions
IRS Pin Full-Scale Input
V
DDA
2.0V
P-P
V
SSA
1.5V
P-P
Floating 1.0V
P-P
OUTPUT PINS
The ADC10065 has 10 TTL/CMOS compatible Data Output pins. The offset binary data is present at these
outputs while the DF and STBY pins are low. Be very careful when driving a high capacitance bus. The more
capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows
through V
DDIO
and V
SSIO
. These large charging current spikes can cause on-chip noise and couple into the
analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful
attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 10
pF/pin will cause t
OD
to increase, making it difficult to properly latch the ADC output data. The result could be an
apparent reduction in dynamic performance. To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by minimizing load capacitance and by connecting buffers
between the ADC outputs and any other circuitry, which will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could otherwise result in performance degradation. Only one
driven input should be connected to the ADC output pins.
While the t
OD
time provides information about output timing, a simple way to capture a valid output is to latch the
data on the rising edge of the conversion clock.
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