Datasheet

ADC10040
www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for V
SSA
= V
SSIO
= 0V, V
DDA
= +3.0V, V
DDIO
= +2.5V, V
IN
= 2 V
P-P
,
STBY = 0V, External V
REF
= 1.20V, f
CLK
= 40 MHz, 50% Duty Cycle, C
L
= 10 pF/pin. Boldface limits apply for T
A
= T
MIN
to
T
MAX
: all other limits T
A
= 25°C
(1)(2)(3)
Symbol Parameter Conditions Min Typ Max Units
CLK, DF, STBY, SENSE
Logical “1” Input Voltage 2 V
Logical “0” Input Voltage 0.8 V
Logical “1” Input Current +10 µA
Logical “0” Input Current −10 µA
D0–D9 OUTPUT CHARACTERISTICS
Logical “1” Output Voltage I
OUT
= −0.5 mA V
DDIO
− 0.2 V
Logical “0” Output Voltage I
OUT
= 1.6 mA 0.4 V
DYNAMIC CONVERTER CHARACTERISTICS
(4)
9.4, 9.6 Bits
f
IN
= 11 MHz
9.3
ENOB Effective Number of Bits
9.4, 9.6 Bits
f
IN
= 19 MHz
9.3
58.7, 59.6 dB
f
IN
= 11 MHz
58.1
SNR Signal-to-Noise Ratio
58.6, 59.5 dB
f
IN
= 19 MHz
58
58.6, dB
f
IN
= 11 MHz 59.5
58
SINAD Signal-to-Noise Ratio + Distortion
58.5, dB
f
IN
= 19 MHz 59.4
57.8
−75.9,
f
IN
= 11 MHz −89 dBc
−74.7
2nd HD 2nd Harmonic
−74.4,
f
IN
= 19 MHz −86 dBc
−73
−69.5,
f
IN
= 11 MHz −78 dBc
−67.5
3rd HD 3rd Harmonic
−68.8,
f
IN
= 19 MHz −77 dBc
−66.7
−69.5,
f
IN
= 11 MHz −78 dB
−67.5
Total Harmonic Distortion (First 6
THD
Harmonics)
−68.8,
f
.IN
= 19 MHz −77 dB
−66.7
−75.8,
f
IN
= 11 MHz −80 dBc
−74.5
Spurious Free Dynamic Range
SFDR
(Excluding 2nd and 3rd Harmonic)
−75.7,
f
IN
= 19 MHz −80 dBc
−74.3
(1) To ensure accuracy, it is required that |V
DDA
–V
DDIO
| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(2) With the test condition for 2 V
P-P
differential input, the 10-bit LSB is 1.95 mV.
(3) Typical figures are at T
A
= T
J
= 25°C and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average
Outgoing Quality Level).
(4) Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V.
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