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ADC10040

www.ti.com

SNAS224M –JULY 2003–REVISED APRIL 2013

ADC10040/ADC10040Q 10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter

Check for Samples: ADC10040

FEATURES

DESCRIPTION

The ADC10040 is a monolithic CMOS analog-to-

• Single +3.0V Operation

digital converter capable of converting analog input

• Selectable 2.0 V

P-P

, 1.5 V

P-P

, or 1.0 V

P-P

full-

signals into 10-bit digital words at 40 Megasamples

scale input swing

per second (MSPS). This converter uses a

• 400 MHz −3 dB Input Bandwidth

differential, pipeline architecture with digital error

correction and an on-chip sample-and-hold circuit to

• Low Power Consumption

provide a complete conversion solution, and to

• Standby Mode

minimize power consumption, while providing

• On-Chip Reference and Sample-and-Hold

excellent dynamic performance. A unique sample-

Amplifier

and-hold stage yields a full-power bandwidth of 400

MHz. Operating on a single 3.0V power supply, this

• Offset Binary or Two’s Complement Data

device consumes just 55.5 mW at 40 MSPS,

Format

including the reference current. The Standby feature

• Separate Adjustable Output Driver Supply to

reduces power consumption to just 13.5 mW.

Accommodate 2.5V and 3.3V Logic Families

The differential inputs provide a full scale selectable

• AEC-Q100 Grade 3 Qualified

input swing of 2.0 V

P-P

, 1.5 V

P-P

, 1.0 V

P-P

, with the

• 28-Pin TSSOP Package

possibility of a single-ended input. Full use of the

differential input is recommended for optimum

performance. An internal +1.2V precision bandgap

KEY SPECIFICATIONS

reference is used to set the ADC full-scale range, and

• Resolution: 10 Bits

also allows the user to supply a buffered referenced

• Conversion Rate: 40 MSPS

voltage for those applications requiring increased

accuracy. The output data format is user choice of

• Full Power Bandwidth: 400 MHz

offset binary or two’s complement.

• DNL: ±0.3 LSB typ)

The ADC10040Q runs on an Automotive Grade Flow

• SNR (f

= 11 MHz): 59.6 dB (typ)

and is AEC-Q100 Grade 3 Qualified.

• SFDR (f

= 11 MHz): -80 dB (typ)

This device is available in the 28-lead TSSOP

• Power Consumption, 40 MHz: 55.5 mW

package and will operate over the industrial

temperature range of −40°C to +85°C.

APPLICATIONS

• Ultrasound and Imaging

• Instrumentation

• Cellular Base Stations/Communications

Receivers

• Sonar/Radar

• xDSL

• Wireless Local Loops

• Data Acquisition Systems

• DSP Front Ends

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 ADC10040/ADC10040Q 10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter Check for Samples: ADC10040 FEATURES DESCRIPTION • • The ADC10040 is a monolithic CMOS analog-todigital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS).
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ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com Connection Diagram Figure 1.
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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 12 VIN− Inverting analog input signal. With a 1.2V reference the full-scale input signal level is a differential 1.0 VP-P. This pin may be tied to VCOM (pin 4) for single-ended operation. 13 VIN+ Non-inverting analog input signal. With a 1.2V reference the fullscale input signal level is a differential 1.0 VP-P.
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ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com Pin Descriptions and Equivalent Circuits (continued) Pin No. Symbol Equivalent Circuit Description 16–20, 23–27 D0–D9 Digital output data. D0 is the LSB and D9 is the MSB of the binary output word. 2, 9, 10 VDDA Positive analog supply pins. These pins should be connected to a quiet 3,0V source and bypassed to analog ground with a 0.1 µF monolithic capacitor located within 1 cm of these pins. A 4.
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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) (3) VDDA, VDDIO 3.9V −0.3V to VDDA or VDDIO +0.3V Voltage on Any Pin to GND Input Current on Any Pin ±25 mA (4) ±50 mA Package Input Current See (5) Package Dissipation at T = 25°C ESD Susceptibility Human Body Model (6) Machine Model 2500V (6) 250V Soldering Temperature Infrared, 10 sec.
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ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, External VREF = 1.20V, fCLK = 40 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, External VREF = 1.20V, fCLK = 40 MHz, 50% Duty Cycle, CL = 10 pF/pin.
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ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P (full scale), STBY = 0V, External VREF = 1.20V, fCLK = 40 MHz, 50% Duty Cycle, CL = 10 pF/pin.
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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC. CONVERSION LATENCY See PIPELINE DELAY.
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ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first six harmonic levels at the output to the level of the fundamental at the output. THD is calculated as: (2) where f1 is the RMS power of the fundamental (output) frequency and f2 through f6 are the RMS power in the first 6 harmonic frequencies.
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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, External VREF = 1.2V, fCLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. Figure 4. DNL Figure 5. DNL vs. fCLK Figure 6. DNL vs. Clock Duty Cycle (DC input) Figure 7. DNL vs. Temperature Figure 8. INL Figure 9. INL vs.
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ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, External VREF = 1.2V, fCLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. 12 Figure 10. INL vs. Clock Duty Cycle Figure 11. SNR vs. VDDIO Figure 12. SNR vs. VDDA Figure 13. SNR vs. fCLK Figure 14. INL vs. Temperature Figure 15. SNR vs.
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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, External VREF = 1.2V, fCLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. Figure 16. SNR vs. Temperature Figure 17. THD vs. VDDA Figure 18. THD vs. VDDIO Figure 19. THD vs. fCLK Figure 20. SNR vs. IRS Figure 21. THD vs.
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ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, External VREF = 1.2V, fCLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. 14 Figure 22. SINAD vs. VDDA Figure 23. SINAD vs. VDDIO Figure 24. THD vs. Clock Duty Cycle Figure 25. SINAD vs. Clock Duty Cycle Figure 26. THD vs. Temperature Figure 27. SINAD vs.
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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, External VREF = 1.2V, fCLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. Figure 28. SINAD vs. fCLK Figure 29. SFDR vs. VDDIO Figure 30. SINAD vs. IRS Figure 31. SFDR vs. fCLK Figure 32. SFDR vs. VDDA Figure 33. SFDR vs.
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ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, External VREF = 1.2V, fCLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. 16 Figure 34. SFDR vs. Clock Duty Cycle Figure 35. Spectral Response @ 11 MHz Input Figure 36. SFDR vs. Temperature Figure 37.
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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The ADC10040 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 10 bits. In differential mode , each analog input signal should have a peak-to-peak voltage equal to 1.0V, 0.75V or 0.5V, depending on the state of the IRS pin (pin 5), and be centered around VCM and be 180° out of phase with each other.
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ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com 2.5V Max VCM + 1V VCM VCM - 1V 0V Min Figure 39. Input Voltage Waveform for a 2VP-P Single Ended Input A single ended input signal is shown in Figure 39. The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving source tries to compensate for this, it adds noise to the signal.
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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 OUTPUT PINS The ADC10040 has 10 TTL/CMOS compatible Data Output pins. The offset binary data is present at these outputs while the DF and STBY pins are low. Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDDIO and VSSIO.
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ADC10040 SNAS224M – JULY 2003 – REVISED APRIL 2013 www.ti.com D.C. Applications For very low frequency and DC input applications, a d.c. coupled amplifier or buffer may be needed, especially when the input is single-ended and the advantages of a differential input signal is desired. Figure 41 shows the input drive circuit that can be used to replace the transformer of Figure 40. The LMH6550 provides excellent performance and is well-suited for this application.
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ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision L (April 2013) to Revision M • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC10040CIMTX/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 ADC10040QCIMTX/NOPB TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC10040CIMTX/NOPB TSSOP PW 28 2500 367.0 367.0 38.0 ADC10040QCIMTX/NOPB TSSOP PW 28 2500 367.0 367.0 38.
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