Datasheet

ADC08L060
SNAS167G –MAY 2002–REVISED MARCH 2013 www.ti.com
Converter Electrical Characteristics (continued)
The following specifications apply for V
A
= V
DR
= +3.0V
DC
, V
RT
= +1.9V, V
RB
= 0.3V, C
L
= 10 pF, f
CLK
= 60 MHz at 50% duty
cycle. Boldface limits apply for T
J
= T
MIN
to T
MAX
: all other limits T
J
= 25°C
(1)(2) (3)
Typical Limits Units
Symbol Parameter Conditions
(4) (4)
(Limits)
CLK, PD DIGITAL INPUT CHARACTERISTICS
V
IH
Logical High Input Voltage V
DR
= V
A
= 3.6V 2.0 V (min)
V
IL
Logical Low Input Voltage V
DR
= V
A
= 2.7V 0.8 V (max)
I
IH
Logical High Input Current V
IH
= V
DR
= V
A
= 3.6V 10 nA
I
IL
Logical Low Input Current V
IL
= 0V, V
DR
= V
A
= 2.7V −50 nA
C
IN
Logic Input Capacitance 3 pF
DIGITAL OUTPUT CHARACTERISTICS
V
OH
High Level Output Voltage V
A
= V
DR
= 2.7V, I
OH
= −400 µA 2.6 2.4 V (min)
V
OL
Low Level Output Voltage V
A
= V
DR
= 2.7V, I
OL
= 1.0 mA 0.4 0.5 V (max)
DYNAMIC PERFORMANCE
f
IN
= 10.1 MHz, V
IN
= FS − 0.25 dB 7.6 6.9 Bits (min)
ENOB Effective Number of Bits
f
IN
= 29 MHz, V
IN
= FS − 0.25 dB 7.4 Bits
f
IN
= 10.1 MHz, V
IN
= FS − 0.25 dB 47.4 43.3 dB (min)
SINAD Signal-to-Noise & Distortion
f
IN
= 29 MHz, V
IN
= FS − 0.25 dB 46.1 dB
f
IN
= 10.1 MHz, V
IN
= FS − 0.25 dB 48 44.5 dB (min)
SNR Signal-to-Noise Ratio
f
IN
= 29 MHz, V
IN
= FS − 0.25 dB 47.2 dB
f
IN
= 10.1 MHz, V
IN
= FS − 0.25 dB 59.1 dBc
SFDR Spurious Free Dynamic Range
f
IN
= 29 MHz, V
IN
= FS − 0.25 dB 54.5 dBc
f
IN
= 10.1 MHz, V
IN
= FS − 0.25 dB −56.9 dBc
THD Total Harmonic Distortion
f
IN
= 29 MHz, V
IN
= FS − 0.25 dB −53.3 dBc
f
IN
= 10.1 MHz, V
IN
= FS − 0.25 dB -61.1 dBc
HD2 2nd Harmonic Distortion
f
IN
= 29 MHz, V
IN
= FS − 0.25 dB −54.9 dBc
f
IN
= 10.1 MHz, V
IN
= FS − 0.25 dB −64.2 dBc
HD3 3rd Harmonic Distortion
f
IN
= 29 MHz, V
IN
= FS − 0.25 dB −63.1 dBc
f
1
= 11 MHz, V
IN
= FS − 6.25 dB
IMD Intermodulation Distortion −55 dBc
f
2
= 12 MHz, V
IN
= FS − 6.25 dB
POWER SUPPLY CHARACTERISTICS
DC Input 13 15.9 mA (max)
I
A
Analog Supply Current
f
IN
= 10 MHz, V
IN
= FS − 3 dB 14 mA
DC Input 0.04 0.2 mA (max)
DRI
D
Output Driver Supply Current
f
IN
= 10 MHz, V
IN
= FS − 3 dB
(5)
4.2 mA
DC Input 13 16.1 mA (max)
f
IN
= 10 MHz, V
IN
= FS − 3 dB, PD =
I
A
+ DRI
D
Total Operating Current 18.2 mA
Low
CLK Low, PD = Hi 0.33 mA
DC Input 39 48.3 mW (max)
f
IN
= 10 MHz, V
IN
= FS − 3 dB, PD = mW
PC Power Consumption 53
Low
CLK Low, PD = Hi 1 mW
FSE change with 2.7V to 3.3V change in
PSRR
1
Power Supply Rejection Ratio −51 dB
V
A
SNR reduction with 200 mV at 1MHz on
PSRR
2
Power Supply Rejection Ratio 45 dB
supply
(5) I
DR
is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output
pins, the supply voltage, V
DR
, and the rate at which the outputs are switching (which is signal dependent), I
DR
= V
DR
(C
O
x f
O
+ C
1
x f
1
+ … + C
71
x f
7
) where V
DR
is the output driver power supply voltage, C
n
is the total capacitance on any given output pin, and f
n
is the
average frequency at which that pin is toggling.
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