Datasheet

ADC08L060

www.ti.com

SNAS167G –MAY 2002–REVISED MARCH 2013

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must

charge for each conversion, the more instantaneous digital current is required from V

and DR GND. These

large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the

digital data outputs (with a 74F541, for example) may be necessary if the data bus capacitance exceeds 5 pF.

Dynamic performance can also be improved by adding 100Ω series resistors at each digital output, reducing the

energy coupled back into the converter input pins.

Using an inadequate amplifier to drive the analog input. As explained in Section 2.0, the capacitance seen at

the input alternates between 3 pF and 4 pF with the clock. This dynamic capacitance is more difficult to drive

than is a fixed capacitance, and should be considered when choosing a driving device.

Driving the V

pin or the V

pin with devices that can not source or sink the current required by the

ladder. As mentioned in Section 1.0, care should be taken to see that any driving devices can source sufficient

current into the V

pin and sink sufficient current from the V

pin. If these pins are not driven with devices than

can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic

performance.

Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR performance. The use of simple gates with RC timing is generally

inadequate as a clock source.

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