Datasheet

ADC08L060
SNAS167G –MAY 2002–REVISED MARCH 2013 www.ti.com
No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300
mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be
sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than
does the voltage at the ADC08L060 power pins.
THE DIGITAL INPUT PINS
The ADC08L060 has two digital input pins: The PD pin and the Clock pin.
The PD Pin
The Power Down (PD) pin, when high, puts the ADC08L060 into a low power mode where power consumption is
reduced to 1.4 mW with the clock running, or to about 1 mW with the clock held low. Output data is valid and
accurate about 1 microsecond after the PD pin is brought low.
The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is
high.
The ADC08L060 Clock
Although the ADC08L060 is tested and its performance is ensured with a 60 MHz clock, it typically will function
well with clock frequencies from 10 MHz to 80 MHz.
Clock Duty Cycle
The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving
a precise duty cycle is difficult, the ADC08L060 is designed to maintain performance over a range of duty cycles.
While it is specified and performance is ensured with a 50% clock duty cycle and 60 Msps, ADC08L060
performance is typically maintained with clock high and low times of 0.83 ns, corresponding to a clock duty cycle
range of 5% to 95% with a 60 MHz clock. Note that minimum low and high times may not be simultaneously
asserted.
Clock Line Termination
The CLOCK line should be series terminated at the clock source in the characteristic impedance of that line. If
the clock line is longer than
(7)
where t
r
is the clock rise time and t
prop
is the propagation rate of the signal along the trace. The CLOCK pin
should be a.c. terminated with a series RC to ground such that the resistor value is equal to the characteristic
impedance of the clock line and the capacitor value is
(8)
where “L” is the line length in inches and Z
O
is the characteristic impedance of the clock line. Typical t
PROP
is
about 150 ps/inch on FR-4 board material. For FR-4 board material, the value of C becomes
(9)
This termination should be located as close as possible to, but within one centimeter of, the ADC08L060 clock
pin.
LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined
analog and digital ground plane should be used.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise because of the skin effect. Total surface area is more
important than is total ground plane volume. Capacitive coupling between the typically noisy digital circuitry and
the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The
solution is to keep the analog circuitry well separated from the digital circuitry.
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