Datasheet

+
-
200
12
240
47
100
51 pF
Signal
Input
8 11
AGND
D7
13
D6
14
D5
15
D0
22
D1
21
D2
20
D3
19
D4
16
6
3
7
10
V
RT
5
0.1 PF
10 PF
+
+
124 18
0.1 PF
10 PF
V
DR
V
A
Choke
1
V
RB
24
CLK
9
23
PD
+3V
LMH6702
2
17
DR GND
+5V
-3V to -5V
0
.
1
P
F
0
.
1
P
F
10
Gain
Adjust
2.7k
1k1k
0
.
33
P
F
+3V
*
*
Offset Adjust
*
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should enter the ground plane at a
common point.
V
RM
V
IN
7
V
IN
GND
47
ADC08L060
www.ti.com SNAS167G –MAY 2002–REVISED MARCH 2013
The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input
sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but
also on the circuit layout and board material. A resistor value should be chosen between 10Ω and 47Ω and the
capacitor value chose according to the formula
(6)
This will provide optimum SNR performance. Best THD performance is realized when the capacitor and resistor
values are both zero. To optimize SINAD, reduce the capacitor value until SINAD performance is optimized. That
is, until SNR = −THD. This value will usually be in the range of 20& to 65% of the value calculated with the
above formula. An accurate calculation is not possible because of the board material and layout dependence.
The circuit of Figure 32 has both gain and offset adjustments. If you eliminate these adjustments normal circuit
tolerances may result in signal clipping unless care is exercised in the worst case analysis of component
tolerances and the input signal excursion is appropriately limited to account for the worst case conditions.
A. The input amplifier should incorporate some gain for best performance (see text).
Figure 32. Input Amplifier
POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power
pins, with a 0.1 µF ceramic chip capacitor placed within one centimeter of the converter's power supply pins.
Leadless chip capacitors are preferred because they have low lead inductance.
While a single voltage source is recommended for the V
A
and V
DR
supplies of the ADC08L060, these supply pins
should be well isolated from each other to prevent any digital noise from being coupled into the analog portions
of the ADC. A choke or 27Ω resistor is recommended between these supply lines with adequate bypass
capacitors close to the supply pins.
As is the case with all high speed converters, the ADC08L060 should be assumed to have little power supply
rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any
system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other
analog circuitry.
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