Datasheet
8 11
AGN
D
D7
13
D6
14
D5
15
D0
22
D1
21
D2
20
D3
19
D4
16
6
3
+3V
24.9
5 17
DR
GND
10
V
R
T
V
IN
10 PF
+
34.8
2
V
RB
24
CLK
0.1 PF
9
23
PD
0.1 PF
10 PF
+
+
1 4 18
0.1 PF
10 PF
V
D
R
V
A
Chok
e
0.1 PF
10 PF
+
12
+3V
1
%
1
%
0.1 PF
1.5V,
nominal
7
V
IN
GND
ADC08L060
www.ti.com
SNAS167G –MAY 2002–REVISED MARCH 2013
FUNCTIONAL DESCRIPTION
The ADC08L060 uses a unique architecture that achieves over 7 effective bits at input frequencies up to and
beyond Nyquist.
The analog input signal that is within the voltage range set by V
RT
and V
RB
is digitized to eight bits. Input voltages
below V
RB
will cause the output word to consist of all zeroes. Input voltages above V
RT
will cause the output word
to consist of all ones.
Incorporating a switched capacitor bandgap, the ADC08L060 exhibits a power consumption that is proportional to
frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent
performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit
needs.
Data is acquired at the rising edge of the clock and the digital equivalent of that data is available at the digital
outputs 5 clock cycles plus t
OD
later. The ADC08L060 will convert as long as an adequate clock signal is present
at pin 24. The output coding is straight binary.
The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in
the power down mode, where the output pins hold the last conversion before the PD pin went high and the
device consumes about 1.4 mW. Holding the clock input low will further reduce the power consumption in the
power down mode to about 1 mW
APPLICATION INFORMATION
REFERENCE INPUTS
The reference inputs V
RT
and V
RB
are the top and bottom of the reference ladder, respectively. Input signals
between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should
be within the range specified in the Operating Ratings table. Any device used to drive the reference pins should
be able to source sufficient current into the V
RT
pin and sink sufficient current from the V
RB
pin to keep these
voltages stable.
A. Because of the ladder and external resistor tolerances, the reference voltage of this circuit can vary too much for
some applications.
Figure 30. Simple, Low Component Count Reference Biasing
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