Datasheet
ADC088S022
www.ti.com
SNAS341F –SEPTEMBER 2005–REVISED MARCH 2013
ADC088S022 Converter Electrical Characteristics
(1)
(continued)
The following specifications apply for V
A
= V
D
= +2.7V to +5.25V, AGND = DGND = 0V, f
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
=
50 ksps to 200 ksps, and C
L
= 50pF, unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits
(2)
Units
POWER SUPPLY CHARACTERISTICS (C
L
= 10 pF)
2.7 V (min)
V
A
, V
D
Analog and Digital Supply Voltages V
A
≥ V
D
5.25 V (max)
V
A
= V
D
= +2.7V to +3.6V,
0.3 0.74 mA (max)
f
SAMPLE
= 200 kSPS, f
IN
= 40 kHz
Total Supply Current Normal Mode
(CS low)
V
A
= V
D
= +4.75V to +5.25V,
1.1 1.55 mA (max)
f
SAMPLE
= 200 kSPS, f
IN
= 40 kHz
I
A
+ I
D
V
A
= V
D
= +2.7V to +3.6V,
10 nA
f
SCLK
= 0 ksps
Total Supply Current Shutdown Mode
(CS high)
V
A
= V
D
= +4.75V to +5.25V,
30 nA
f
SCLK
= 0 ksps
V
A
= V
D
= +3.0V, f
SAMPLE
= 200 kSPS,
0.9 2.2 mW (max)
f
IN
= 40 kHz
Power Consumption Normal Mode
(CS low)
V
A
= V
D
= +5.0V, f
SAMPLE
= 200 kSPS,
5.5 7.8 mW (max)
P
C
f
IN
= 40 kHz
V
A
= V
D
= +3.0V, f
SCLK
= 0 ksps 0.03 µW
Power Consumption Shutdown Mode
(CS high)
V
A
= V
D
= +5.0V, f
SCLK
= 0 ksps 0.15 µW
AC ELECTRICAL CHARACTERISTICS
f
SCLK
MIN Minimum Clock Frequency 0.8 MHz (min)
f
SCLK
Maximum Clock Frequency 16 3.2 MHz (max)
50 ksps (min)
Sample Rate
f
S
Continuous Mode
1000 200 ksps (max)
t
CONVERT
Conversion (Hold) Time 13 SCLK cycles
30 40 % (min)
DC SCLK Duty Cycle
70 60 % (max)
t
ACQ
Acquisition (Track) Time 3 SCLK cycles
Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles
t
AD
Aperture Delay 4 ns
ADC088S022 Timing Specifications
The following specifications apply for V
A
= V
D
= +2.7V to 5.25V, AGND = DGND = 0V, f
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
=
50 ksps to 200 ksps, and C
L
= 50pF. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits
(1)
Units
t
CSH
CS Hold Time after SCLK Rising Edge 0 10 ns (min)
t
CSS
CS Setup Time prior to SCLK Rising Edge 5 10 ns (min)
t
EN
CS Falling Edge to DOUT enabled 5 30 ns (max)
t
DACC
DOUT Access Time after SCLK Falling Edge 17 27 ns (max)
t
DHLD
DOUT Hold Time after SCLK Falling Edge 4 ns (typ)
t
DS
DIN Setup Time prior to SCLK Rising Edge 3 10 ns (min)
t
DH
DIN Hold Time after SCLK Rising Edge 3 10 ns (min)
t
CH
SCLK High Time 0.4 x t
SCLK
ns (min)
t
CL
SCLK Low Time 0.4 x t
SCLK
ns (min)
DOUT falling 2.4 20 ns (max)
t
DIS
CS Rising Edge to DOUT High-Impedance
DOUT rising 0.9 20 ns (max)
(1) Tested limits are ensured to AOQL (Average Outgoing Quality Level).
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