Datasheet

ADC088S022

SNAS341F –SEPTEMBER 2005–REVISED MARCH 2013

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During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13

SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock

out leading zeros, falling edges 5 through 12 clock out the conversion result, MSB first, and falling edges 13

through 16 clock out trailing zeros. If there is more than one conversion in a frame (continuous conversion

mode), the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK

and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK. "N" is an integer value.

The ADC088S022 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high

and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with

SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as

the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters

track mode. While there is no timing restriction with respect to the rising edges of CS and SCLK, see Figure 3 for

setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.

While a conversion is in progress, the address of the next input for conversion is clocked into a control register

through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. See Table 1, Table 2, and Table 3.

There is no need to incorporate a power-up delay or dummy conversion as the ADC088S022 is able to acquire

the input signal to full resolution in the first conversion immediately following power-up. The first conversion result

after power-up will be that of IN0.

Table 1. Control Register Bits

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

Table 2. Control Register Bit Descriptions

Bit #: Symbol: Description

7, 6, 2, 1, 0 DONTC Don't care. The values of these bits do not affect the device.

5 ADD2

These three bits determine which input channel will be sampled and converted at the next

4 ADD1

conversion cycle. The mapping between codes and channels is shown in Table 3.

3 ADD0

Table 3. Input Channel Selection

ADD2 ADD1 ADD0 Input Channel

0 0 0 IN0 (Default)

0 0 1 IN1

0 1 0 IN2

0 1 1 IN3

1 0 0 IN4

1 0 1 IN5

1 1 0 IN6

1 1 1 IN7

Product Folder Links: ADC088S022