Datasheet

ADC08831, ADC08832
SNAS015C –SEPTEMBER 1999–REVISED MARCH 2013 www.ti.com
Electrical Characteristics (continued)
The following specifications apply for V
CC
= V
REF
= +5V
DC
, and f
CLK
= 2 MHz unless otherwise specified. Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25°C.
Symbol Parameter Conditions Typical
(1)
Limits
(2)
Units (Limits)
I
OUT
TRI-STATE Output Current V
OUT
= 0V −3.0 μA (max)
V
OUT
= 5V 3.0 μA (max)
I
SOURCE
Output Source Current V
OUT
= 0V −6.5 mA (max)
I
SINK
Output Sink Current V
OUT
= V
CC
8.0 mA (min)
I
CC
Supply Current ADC08831 CLK = V
CC
CS = V
CC
0.6 1.0 mA (max)
CS = LOW 1.7 2.4 mA (max)
I
CC
Supply Current ADC08832 CLK = CS = V
CC
1.3 1.8 mA (max)
V
CC
(8)
CS = LOW 2.4 3.5 mA (max)
(8) For the ADC08832 V
ref
is internally tied to V
CC
, therefore, for the ADC08832 reference current is included in the supply current.
Electrical Characteristics
The following specifications apply for V
CC
= V
REF
= +5 V
DC
, and t
r
= t
f
= 20 ns unless otherwise specified. Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25°C.
Symbol Parameter Conditions Typical
(1)
Limits
(2)
Units (Limits)
f
CLK
Clock Frequency 2 MHz (max)
Clock Duty Cycle
(3)
40 % (min)
60 % (max)
T
C
Conversion Time (Not Including MUX f
CLK
= 2MHz 8 1/f
CLK
(max)
Addressing Time) 4 μs (max)
t
CA
Acquisition Time ½ 1/f
CLK
(max)
t
SET-UP
CS Falling Edge or Data Input 25 ns (min)
Valid to CLK Rising Edge
t
HOLD
Data Input Valid after CLK 20 ns (min)
Rising Edge
t
pd1
, t
pd0
CLK Falling Edge to Output Data Valid
(4)
C
L
= 100 pF:
Data MSB First 250 ns (max)
Data LSB First 200 ns (max)
t
1H
, t
0H
TRI-STATE Delay from Rising Edge C
L
= 10 pF, R
L
= 10 kΩ 50 ns
of CS to Data Output and SARS Hi-Z (see TRI-STATE Test Circuits and
Waveforms)
C
L
= 100 pF, R
L
= 2 kΩ 180 ns (max)
C
IN
Capacitance of Analog Input
(5)
13 pF
C
IN
Capacitance of Logic Inputs 5 pF
C
OUT
Capacitance of Logic Outputs 5 pF
(1) Typicals are at T
J
= 25°C and represent the most likely parametric norm.
(2) Specified to TI's AOQL (Average Outgoing Quality Level).
(3) A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle
outside of these limits the minimum time the clock is high or low must be at least 250 ns. The maximum time the clock can be high or
low is 60 μs.
(4) Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow
for comparator response time.
(5) Analog inputs are typically 300 ohms input resistance to a 13pF sample and hold capacitor.
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