Datasheet

ADC08831, ADC08832
www.ti.com SNAS015C –SEPTEMBER 1999–REVISED MARCH 2013
The differential input of these converters actually reduces the effects of common-mode input noise, a signal
common to both selected “+” and “−” inputs for a conversion (60 Hz is most typical). The time interval between
sampling the “+” input and then the “−” input is ½ of a clock period. The change in the common-mode voltage
during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:
where
• where f
CM
is the frequency of the common-mode signal
• V
PEAK
is its peak voltage value
• f
CLK
is the A/D clock frequency (1)
For a 60Hz common-mode signal to generate a ¼ LSB error (≊5mV) with the converter running at 250kHz, its
peak value would have to be 6.63V which would be larger than allowed as it exceeds the maximum analog input
limits.
Source resistance limitation is important with regard to the DC leakage currents of the input multiplexer. Bypass
capacitors should not be used if the source resistance is greater than 1kΩ. The worst-case leakage current of
±1μA over temperature will create a 1mV input error with a 1kΩ source resistance. An op amp RC active low
pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be
required.
Sample and Hold
The ADC08831/2 provide a built-in sample-and-hold to acquire the input signal. The sample and hold can sample
input signals in either single-ended or pseudo differential mode.
Input Op Amps
When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time. To
achieve the full sampling rate, the analog input should be driven with a low impedance source (100Ω) or a high-
speed op amp such as the LM6142. Higher impedance sources or slower op amps can easily be accommodated
by allowing more time for the analog input to settle.
Source Resistance
The analog inputs of the ADC08831/2 look like a 13pF capacitor (C
IN
) in series with 300Ω resistor (Ron). C
IN
gets
switched between the selected “+” and “−” inputs during each conversion cycle. Large external source resistors
will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the
analog input to completely settle.
Board Layout Consideration, Grounding and Bypassing:
The ADC08831/2 are easy to use with some board layout consideration. They should be used with an analog
ground plane and single-point grounding techniques. The GND pin should be tied directly to the ground plane.
The supply pin should be bypassed to the ground plane with a surface mount or ceramic capacitor with leads as
short as possible. All analog inputs should be referenced directly to the single-point ground. Digital inputs and
outputs should be shielded from and routed away from the reference and analog circuitry.
OPTIONAL ADJUSTMENTS
Zero Error
The offset of the A/D does not require adjustment. If the minimum analog input voltage value, V
IN(MIN)
, is not
ground a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum
input voltage by biasing any V
IN
(−) input at this V
IN(MIN)
value. This utilizes the differential mode operation of the
A/D.
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Product Folder Links: ADC08831 ADC08832