Datasheet

IN1
IN4
MUX
T/H
SCLK
V
A
GND
CS
DIN
DOUT
CONTROL
LOGIC
SUCCESSIVE
APPROXIMATION
ADC
.
.
.
GND
8-Bit
1
2
3
4
5
6
7
8
9
10
CS SCLK
DOUT
DIN
IN1
GND
IN4
IN3 IN2
V
A
ADC084S021
ADC084S021
SNAS279E –APRIL 2005–REVISED MARCH 2013 www.ti.com
Connection Diagram
Figure 1. 10-Lead VSSOP
See DGK Package
Block Diagram
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Description
ANALOG I/O
4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to V
A
.
DIGITAL I/O
10 SCLK Digital clock input. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out at this pin on falling edges of the
9 DOUT
SCLK pin.
Digital data input. The ADC084S021's Control Register is loaded through this pin on rising
8 DIN
edges of SCLK.
Chip select. A conversion begins at the falling edge of CS. Conversions continue as long as
1 CS
CS is held low.
POWER SUPPLY
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and be
2 V
A
bypassed to GND with a 0.1 µF monolithic capacitor located within 1 cm of the power pin
and with a 1 µF capacitor.
3 GND Device ground return for all signals.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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