Datasheet

ADC084S021
www.ti.com SNAS279E –APRIL 2005–REVISED MARCH 2013
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when
CS is high and is active when CS is low. CS thus acts as an output enable, in addition to being a start
conversion input. Additionally, the device goes into a power down state when CS is high and between continuous
conversion cycles.
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting with the 5th clock. If
there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK
after the N*16th rising edge of SCLK, and re-enter the hold/convert mode at the N*16+4th falling edge of SCLK,
where "N" is an integer.
SCLK is internally gated off when CS is high. If SCLK is stopped in the low state while CS is high, the
subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track
mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC
enters the track mode at the first falling edge of SCLK after the falling edge of CS.
During each conversion, data is clocked into the device at the DIN pin on the first 8 rising edges of SCLK after
the fall of CS. For each conversion, it is necessary to clock in the data indicating the input that is selected for the
conversion after the current one. That is, the conversion that is started at the fall of CS is of the voltage at the
channel that was selected when the last conversion was started. The first conversion after power up will be of the
first channel. See Table 2, Table 3, and Table 4.
If CS and SCLK go low within the times defined by t
CSU
and t
CLH
, the rising edge of SCLK that begins clocking
data in at DIN may be one clock cycle later than expected. It is, therefore, best to strictly observe the minimum
t
CSU
and t
CLH
times given in ADC084S021 Timing Specifications .
There are no power-up delays or dummy conversions required with the ADC084S021. The ADC is able to
sample and convert an input to full conversion immediately following power up. The first conversion result after
power-up will be that of IN1.
Table 2. Control Register Bits
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC
Table 3. Control Register Bit Descriptions
Bit #: Symbol: Description
7 - 6, 2 - 0 DONTC Don't care. The value of these bits do not affect device operation.
5 ADD2 These three bits determine which input channel will be sampled and converted in the next
track/hold cycle. The mapping between codes and channels is shown in Table 4.
4 ADD1
3 ADD0
Table 4. Input Channel Selection
ADD2 ADD1 ADD0 Input Channel
x 0 0 IN1 (Default)
x 0 1 IN2
x 1 0 IN3
x 1 1 IN4
ADC084S021 TRANSFER FUNCTION
The output format of the ADC084S021 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC084S021 is V
A
/256 and the ideal transfer characteristic is shown
in Figure 48. The transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage
of V
A
/512. Other code transitions occur at steps of one LSB.
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