Datasheet

ADC0844, ADC0848
www.ti.com SNAS523D –JUNE 1999–REVISED MARCH 2013
Figure 24. I/O Interface to NSC800
Sample Program for ADC0848 - NSC800 Interface
0008 NCONV EQU 16
000F DEL EQU 15 ;DELAY 50 µSEC CONVERSION
001F CS EQU 1FH ;THE BOARD ADDRESS
3C00 ADDTA EQU 003CH ;START OF RAM FOR A/D
;DATA
0000' 08 09 0A 0B MUXDTA: DB 08H,09H,0AH,0BH ;MUX DATA
0004' 0C 0D 0E 0F DB 0CH,0DH,0EH,0FH
0008' 0E 1F START: LD C,CS
000A' 06 16 LD B,NCONV
000C' 21 0000' LD HL,MUXDTA
000F' 11 003C LD DE,ADDTA
0012' ED A3 STCONV: OUTI ;LOAD A/D'S MUX DATA
;AND START A CONVERSION
0014' EB EX DE,HL ;HL=RAM ADDRESS FOR THE
;A/D DATA
0015' 3E 0F LD A,DEL
0017' 3D WAIT: DEC A ;WAIT 50 µSEC FOR THE
0018' C2 0013' JP NZ,WAIT ;CONVERSION TO FINISH
001B' ED A2 INI ;STORE THE A/D'S DATA
;CONVERTED ALL INPUTS?
001D' EB EX DE,HL
001E' C2 000E' JP NZ,STCONV ;IF NOT GOTO STCONV
END
Note: This routine sequentially programs the MUX data latch in the signal-ended mode. For CH1-CH8 a
conversion is started, then a 50 μs wait for the A/D to complete a conversion and the data is stored at address
ADDTA for CH1, ADDTA + 1 for CH2, etc.
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