Datasheet

ADC082S021

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SNAS282D –APRIL 2005–REVISED MARCH 2013

Power Management

When the ADC082S021 is operated continuously in normal mode, the maximum throughput is f

SCLK

/16.

Throughput may be traded for power consumption by running f

SCLK

at its maximum 3.2 MHz and performing

fewer conversions per unit time, putting the ADC082S021 into shutdown mode between conversions. A plot of

typical power consumption versus throughput is shown in the Typical Performance Characteristics section. To

calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by

the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the

shutdown mode power consumption. Generally, the user will put the part into normal mode and then put the part

back into shutdown mode. Note that the curve of power consumption vs. throughput is nearly linear. This is

because the power consumption in the shutdown mode is so small that it can be ignored for all practical

purposes.

Power Supply Noise Considerations

The charging of any output load capacitance requires current from the power supply, V

. The current pulses

required from the supply to charge the output capacitance will cause voltage variations on the supply. If these

variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore,

discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current

into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the

substrate that will degrade noise performance if that current is large enough. The larger is the output

capacitance, the more current flows through the die substrate and the greater is the noise coupled into the

analog channel, degrading noise performance.

To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load

capacitance is greater than 50 pF, use a 100 Ω series resistor at the ADC output, located as close to the ADC

output pin as practical. This will limit the charge and discharge current of the output capacitance and improve

noise performance.

Product Folder Links: ADC082S021